Efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 μm CMOS low-voltage applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1999, Pages 65-66

  Ponomarev, Y V ^a   Stolk, P A ^a   van Brandenburg, A C M C ^a   Dachs, C J J ^a   Kaiser, M ^a   Montree, A H ^a   Roes, R ^a   Schmitz, J ^a   Woerlee, P H ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRON TRANSPORT PROPERTIES; GERMANIUM; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; SWITCHING CIRCUITS;

GATE WORK FUNCTION; LOW VOLTAGE OPERATION; SHORT CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0033281380     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)