Low voltage erase technique for DINOR flash memory devices

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1999, Pages 17-18

  Liu, Zhizheng ^a   Ma, T P ^a  

^a YALE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FIELDS; ELECTRIC POTENTIAL; ELECTRONS; MOSFET DEVICES; OXIDES; SUBSTRATES;

ABRUPT DRAIN JUNCTION; FLASH MEMORY DEVICES; FLOATING GATE; GRADE SOURCE JUNCTION; LOW VOLTAGE ERASE TECHNIQUE; PULSE AGITATED SUBSTRATE HOT ELECTRON INJECTION; TUNNEL OXIDE;

DATA STORAGE EQUIPMENT;

EID: 0033281137     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)