3.6Gb/s 340mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1999, Pages 27-30

  Nakura, Toru ^a   Ueda, Kimio ^a   Kubo, Kazuo ^a   Fernandez, Warren ^a   Matsuda, Yoshio ^a   Mashiko, Koichiro ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY; TIMING CIRCUITS;

JUNCTION CAPACITANCES; PIPELINED MULTIPLEXER; SELECTOR CIRCUIT; SILICON ON INSULATOR CMOS TECHNOLOGY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033281016     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)