50 Gb/s 32 × 32 CMOS crossbar chip using asymmetric serial links

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1999, Pages 19-20

  Chang, Kun Yung Ken ^a   Chuang, Shang Tse ^a   McKeown, Nick ^a   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BIT ERROR RATE; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER NETWORKS; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT; NETWORK PROTOCOLS; SYNCHRONIZATION; TELECOMMUNICATION LINKS;

ASSYMETRIC SERIAL LINKS; CMOS MULTI STAGE MULTIPLEXORS; CROSSBAR CHIP; DATA TRANSMISSION PROTOCOL; DUMB TO SMART LINK; SMART TO DUMB LINK;

CMOS INTEGRATED CIRCUITS;

EID: 0033280877     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)