Gate-level voltage scaling for low-power design using multiple supply voltages

IEE Proceedings: Circuits, Devices and Systems

Volumn 146, Issue 6, 1999, Pages 334-339

  Yeh, C ^a   Chang, M C ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION;

GATE-LEVEL VOLTAGE SCALING; MULTIPLE SUPPLY VOLTAGES;

LOGIC GATES;

EID: 0033280258     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19990579     Document Type: Article

References (14)

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