Robust scanbased logic test in VDSM technologies

Computer

Volumn 32, Issue 11, 1999, Pages 66-74

  Wagner, Kenneth D ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

SCAN-BASED LOGIC TESTS;

CONTROLLABILITY; DESIGN FOR TESTABILITY; FORMAL LOGIC; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; ROBUSTNESS (CONTROL SYSTEMS); SCANNING; SEMICONDUCTING SILICON;

INTEGRATED CIRCUIT TESTING;

EID: 0033221974     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.803644     Document Type: Article

References (2)

1. A. Kobayashi, S. Matsue, and H. Shiba, "Flip-Flop Circuits with Fault Location Test Capability," Proc. IECEJ Nat'l Convention, 1968, p. 962.
2. S. Funatsu, M. Kawai, and A. Yamada, "Scan Design at NEC," IEEE Design & Test of Computers, June 1989, pp. 50-57.