Implementation of high speed Viterbi detectors

Electronics Letters

Volumn 35, Issue 24, 1999, Pages 2089-2090

  Conway, T ^a  

^a UNIVERSITY OF LIMERICK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FLIP FLOP CIRCUITS; PARALLEL PROCESSING SYSTEMS;

VITERBI ALGORITHM;

DETECTOR CIRCUITS;

EID: 0033221681     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19991413     Document Type: Article

References (5)

1. FORNEY, G.D.: 'Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference', IEEE Trans., 1972, IT-18, pp. 363-378
2. BLACK, P.J., and MENG, T.H.: 'A 140-Mb/s, 32-state, radix-4 Viterbi decoder', IEEE J. Solid-State Circuits, 1992, SC-27, pp. 1877-1885
3. FETTWEIS, G.P., KARABED, R., SEIGEL, P., and THAPAR, H.: 'Method and means for detecting partial response waveforms using a modified dynamic programming heuristic'. United States Patent 5,430,744, July 4, 1995
4. THAPAR, H.K., and PATEL, A.M.: 'A class of partial response systems for increasing storage density in magnetic recording', IEEE Trans., 1987, MAG-23, (5), pp. 3666-3668
5. HEKSTRA, A.P.: 'An alternative to metric rescaling in Viterbi decoders', IEEE Trans., 1989, COM-37, (11), pp. 1220-1222