메뉴 건너뛰기




Volumn 48, Issue 10, 1999, Pages 1138-1144

On the yield of VLSI processors with on-chip CPU cache

Author keywords

Fault tolerance; On chip CPU caches; Partially good chips; Yield enhancement

Indexed keywords

BENCHMARKING; BUFFER STORAGE; MICROPROCESSOR CHIPS; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER); VLSI CIRCUITS;

EID: 0033204755     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.805163     Document Type: Article
Times cited : (7)

References (20)
  • 1
    • 0025457747 scopus 로고
    • Fault Tolerance in VLSI Circuits
    • July
    • I. Koren and A.D. Singh, "Fault Tolerance in VLSI Circuits," Computer, pp. 73-83, July 1990.
    • (1990) Computer , pp. 73-83
    • Koren, I.1    Singh, A.D.2
  • 2
    • 0019013812 scopus 로고
    • Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product
    • C.H. Stapper, A.N. McLaren, and M. Dreckmann, "Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product," IBM J. Research and Development, vol. 20, pp. 398-409, 1980.
    • (1980) IBM J. Research and Development , vol.20 , pp. 398-409
    • Stapper, C.H.1    McLaren, A.N.2    Dreckmann, M.3
  • 3
    • 33646929615 scopus 로고
    • Block Alignment: A Method for Increasing the Yield of Memory Chips that Are Partially Good
    • I. Koren, ed., New York: Plenum
    • C.H. Stapper, "Block Alignment: A Method for Increasing the Yield of Memory Chips that Are Partially Good," Defect and Fault Tolerance in VLSI Systems, I. Koren, ed., pp. 243-255, New York: Plenum, 1989.
    • (1989) Defect and Fault Tolerance in VLSI Systems , pp. 243-255
    • Stapper, C.H.1
  • 5
    • 0026854257 scopus 로고
    • The MIPS R4000 Processor
    • Apr.
    • S. Miraburi et al., "The MIPS R4000 Processor," IEEE Micro, pp. 10-22, Apr. 1992.
    • (1992) IEEE Micro , pp. 10-22
    • Miraburi, S.1
  • 6
    • 0029292848 scopus 로고
    • Superscalar Instruction Execution in the 21164 Alpha Microprocessor
    • Apr.
    • J.H. Edmodson et al., "Superscalar Instruction Execution in the 21164 Alpha Microprocessor," IEEE Micro, pp. 33-43, Apr. 1995.
    • (1995) IEEE Micro , pp. 33-43
    • Edmodson, J.H.1
  • 7
    • 34250838159 scopus 로고
    • Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors
    • Apr.
    • G. Sohi, "Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors," IEEE Trans. Computers, vol. 38, no. 4, pp. 484-492, Apr. 1989.
    • (1989) IEEE Trans. Computers , vol.38 , Issue.4 , pp. 484-492
    • Sohi, G.1
  • 8
    • 0027556820 scopus 로고
    • Performance Implications of Tolerating Cache Faults
    • Mar.
    • A.F. Pour and M.D. Hill, "Performance Implications of Tolerating Cache Faults," IEEE Trans. Computers, vol. 42, no. 3, pp. 257-267, Mar. 1993.
    • (1993) IEEE Trans. Computers , vol.42 , Issue.3 , pp. 257-267
    • Pour, A.F.1    Hill, M.D.2
  • 10
    • 0029212963 scopus 로고
    • Performance Recovery in Direct-Mapped Faulty Caches via the Use of a Very Small Fully Associative Spare Cache
    • Erlangen, Germany, Apr.
    • H.T. Vergos and D. Nikolos, "Performance Recovery in Direct-Mapped Faulty Caches via the Use of a Very Small Fully Associative Spare Cache," Proc. IEEE Int'l Computer Performance and Dependability Symp. (IPDS '95), pp. 326-332, Erlangen, Germany, Apr. 1995.
    • (1995) Proc. IEEE Int'l Computer Performance and Dependability Symp. (IPDS '95) , pp. 326-332
    • Vergos, H.T.1    Nikolos, D.2
  • 12
    • 0023362112 scopus 로고
    • Designing Interconnection Buses in VLSI and WSI for Maximum Yield and Minimum Delay
    • June
    • I. Koren, Z. Koren, and D.K. Pradhan, "Designing Interconnection Buses in VLSI and WSI for Maximum Yield and Minimum Delay," IEEE J. Solid-State Circuits, vol. 23, no. 3, pp. 859-865, June 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.23 , Issue.3 , pp. 859-865
    • Koren, I.1    Koren, Z.2    Pradhan, D.K.3
  • 13
    • 0002322314 scopus 로고
    • Yield Models for Defect-Tolerant VLSI Circuits: A Review
    • I. Koren, ed., New York: Plenum
    • I. Koren and C.H. Stapper, "Yield Models for Defect-Tolerant VLSI Circuits: A Review," Defect and Fault Tolerance in VLSI Systems, vol. 1, pp. 1-21, I. Koren, ed., New York: Plenum, 1989.
    • (1989) Defect and Fault Tolerance in VLSI Systems , vol.1 , pp. 1-21
    • Koren, I.1    Stapper, C.H.2
  • 15
    • 0003650381 scopus 로고
    • An Enhanced Access and Cycle Time Model for On-Chip Caches
    • DEC Western Research Lab
    • S.J.E. Wilton and N.P. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," Technical Report 93/5, DEC Western Research Lab, 1994.
    • (1994) Technical Report 93/5
    • Wilton, S.J.E.1    Jouppi, N.P.2
  • 16
    • 0026103250 scopus 로고
    • An Area Model for On-Chip Memories and its Application
    • Feb.
    • J.M. Mulder, N.T. Quach, and M.J. Flynn, "An Area Model for On-Chip Memories and its Application," IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 98-106, Feb. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.2 , pp. 98-106
    • Mulder, J.M.1    Quach, N.T.2    Flynn, M.J.3
  • 17
    • 0025479673 scopus 로고
    • Testability Features of the 68040
    • Washington, D.C., Sept.
    • M.G. Gallup et al., "Testability Features of the 68040," Proc. Int'l Test Conf., pp. 749-757, Washington, D.C., Sept. 1990.
    • (1990) Proc. Int'l Test Conf. , pp. 749-757
    • Gallup, M.G.1
  • 18
    • 0029252322 scopus 로고
    • Fault-Tolerant Features in the HaL Memory Management Unit
    • Feb.
    • N.R. Saxena et al., "Fault-Tolerant Features in the HaL Memory Management Unit," IEEE Trans. Computers, vol. 44, no. 2, pp. 170-179, Feb. 1995.
    • (1995) IEEE Trans. Computers , vol.44 , Issue.2 , pp. 170-179
    • Saxena, N.R.1
  • 19
    • 0022721282 scopus 로고
    • A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yield
    • May
    • W.R. Moore, "A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yield," Proc. IEEE, vol. 74, no. 4, pp. 684-698, May 1986.
    • (1986) Proc. IEEE , vol.74 , Issue.4 , pp. 684-698
    • Moore, W.R.1
  • 20
    • 0029230167 scopus 로고
    • Circuit Implementation of a 300-MHz 64-bit Second-Generation CMOS Alpha CPU
    • W.J. Bowhill et al., "Circuit Implementation of a 300-MHz 64-bit Second-Generation CMOS Alpha CPU," Digital Technical J., vol. 7, no.1, pp.100-117, 1995.
    • (1995) Digital Technical J. , vol.7 , Issue.1 , pp. 100-117
    • Bowhill, W.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.