A generalized hspice™ macro-model for pinned spin-dependent-tunneling devices

IEEE Transactions on Magnetics

Volumn 35, Issue 5 PART 1, 1999, Pages 2889-2891

  Das, Bodhisattva ^a   Black, William C ^b  

^a IEEE   (United States)

^b Iowa State University of Science and Technology   (United States)

Author keywords

Circuit macro model; MRAM; Piece wise linear (PWL); Pinned SDT

Indexed keywords

SOFTWARE PACKAGE HSPICE; SPIN-DEPENDENT-TUNNELING DEVICES;

COMPUTER SIMULATION; MATHEMATICAL MODELS; PIECEWISE LINEAR TECHNIQUES; RANDOM ACCESS STORAGE;

MAGNETIC STORAGE;

EID: 0033183875     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/20.801015     Document Type: Article

References (4)

1. HSPICE is a registered trademark of Avant! Corporation.
2. B. Das, W. C. Black, Jr., and A. V. Pohm, "A Universal HSPICE Macro-Model for GMR Memory Bits," submitted to IEEE Transactions on Magnetics, December 1998.
3. rd ed., Oxford University Press.
4. W. C. Black Jr., and R. T. Fayfield, "High-Speed Circuits Employing On-Chip Magnetic Components," presented at the 1999 Southwest Symposium on Mixed-Signal Design, April 11-13, 1999, Tucson, AZ, U.S.A.