BiCMOS active substrate probe-card technology for digital testing

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 8, 1999, Pages 1118-1135

  Zargari, Masoud ^a,b,d,e,f,g   Leung, Justin ^a,c   Wong, S Simon ^a,h   Wooley, Bruce A ^a  

^a Stanford University   (United States)

^b T Span Systems Corp   (United States)

^c INTEL CORPORATION   (United States)

^d Brooktree Corp   (United States)

^e SONY CORPORATION   (Japan)

^f HDAC Inc   (United States)

^g Wireless Access Inc   (United States)

^h School of Operations Research and Industrial Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; TIMING CIRCUITS;

AUTOMATIC TEST EQUIPMENT; DIGITAL TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0033169540     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.777110     Document Type: Article

References (14)

1. M. R. Barber, "Subnanosecond timing measurements on MOS devices using modern VLSI test systems," in 1983 Int. Test Conf. Dig. Tech. Papers, pp. 170-180.
2. M. Zargari, "A BiCMOS active substrate probe card technology for digital testing," Ph.D. dissertation, Stanford University, Stanford, CA, Mar. 1997.
3. M. Beiley, J. Leung, and S. S. Wong, "A micromachined array probe card - Fabrication process," IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 18, pp. 179-183, Feb. 1995.
4. _, "A micromachined array probe card - Characterization," IEEE Trans. Camp., Packag., Manufact. Technol. B, vol. 18, pp. 184-191, Feb. 1995.
5. M. Zargari and B. A. Wooley, "A BiCMOS active pull-down ECL output driver for low power applications," in 1995 IEEE Symp. Low Power Electronics Dig. Tech. Papers, pp. 50-51.
6. The Stanford BiCMOS Project Annual Report, Center for Integrated Systems, Stanford University, Stanford, CA, 1990, pp. 7-24.
7. J. Miyamoto and M. Horowitz, "A single-chip LSI high-speed functional tester," IEEE J. Solid-State Circuits, vol. SC-22, pp. 820-828, Oct. 1987.
8. J. A. Gasbarro and M. A. Horowitz, "Integrated pin electronics for VLSI functional testers," IEEE J. Solid-State Circuits, vol. 24, pp. 331-337, Apr. 1989.
9. J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
10. T. Knotts, D. Chu, and J. Sommer, "A 500 MHz time digitizer IC with 15.625 ps resolution," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 58-59.
11. J. G. Maneatis, "Precise delay generation using coupled oscillators," Ph.D. dissertation, Stanford University, Stanford, CA, June 1994.
12. J. P. Hein and J. W. Scott, "z-domain model for discrete-time PLL's," IEEE Trans. Circuits Syst., vol. 35, pp. 1393-1399, Nov. 1988.
13. C. A. Sharpe, "A 3-State phase detector can improve your next PLL design," EDN Mag., Sept. 20, 1976.
14. M. J. Demler, High-Speed Analog to Digital Conversion. San Diego, CA: Academic, 1991.