New tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability?

Microelectronics Reliability

Volumn 39, Issue 6-7, 1999, Pages 731-739

  McDonald, Chris J ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA MINING; DEFECTS; ELECTRONICS PACKAGING; INSPECTION; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; QUALITY CONTROL; RELIABILITY; SILICON WAFERS; YIELD STRESS;

AUTOMATIC DEFECT CLASSIFICATION; PROBE YIELD; YIELD;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033143221     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(99)00094-3     Document Type: Article

References (29)

1. R. C. Leachman, Editor, "The Competitive Semiconductor Manufacturing Survey: Second Report on Results of the Main Phase," University of California at Berkeley, Center for Research in Management, 1994. R.C. Leachman and D. Hodges, "Benchmarking Semiconductor Manufacturing," IEEE Trans. Semiconductor Manufacturing, Vol. 9, No. 2, May 1996, pp. 158-169. See also http://euler.berkeley.edu/ersu/csm/csmreports.htm
2. R. C. Leachman, Editor, "The Competitive Semiconductor Manufacturing Survey: Second Report on Results of the Main Phase," University of California at Berkeley, Center for Research in Management, 1994. R.C. Leachman and D. Hodges, "Benchmarking Semiconductor Manufacturing," IEEE Trans. Semiconductor Manufacturing, Vol. 9, No. 2, May 1996, pp. 158-169. See also http://euler.berkeley.edu/ersu/csm/csmreports.htm
3. th 1995
4. J.A. Cunningham, "The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing," in IEEE Trans. On Semiconductor Manufacturing, Vol. 3, No. 2, pp. 60-71.
5. C.H. Stapper, R.M. Armstrong, and K. Saji, "Integrated Circuit Yield Statistics," in Proc. IEEE 71(4), April 1983, pp. 453-470.
6. C. Mallory, D. Perloff, T. Hasan and R. Stanley, "Special Yield Analysis in Integrated Circuit Manufacturing," Solid State Technology, November 1983.
7. B.T. Murphy, "Cost Size Optima of Monolithic Integrated Circuits," in Proc. of IEEE, Vol 52, No. 12, December 1964, pp. 1537-1545.
8. R. B. Seeds, "Yield and Cost Analysis of Bipolar LSI," presented at IEEE International Electron Devices Meeting, Washington, October 1967.
9. W.C. Riordan, R. Miller, J. M. Sherman and J. Hicks, "Microprocessor Reliability Performance as a Function of Die Location for a 0.25μm, Five-Layer Metal CMOS Logic Process," presented at the International Reliability Physics Symposium, 1999
10. C. H. Stapper and R.J. Rosner, "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation," IEEE Trans. Semiconductor Manufacturing, Vol. 8, No. 2, May 1995.
11. P.K. Nag, W. Maly and H.J. Jacobs, "Simulation of Yield/Cost Learning Curves with Y4," IEEE Trans. Semiconductor Manufacturing, Vol. 10, No. 2, May 1997, p. 256.
12. C. Radin, "A Defect Reduction Methodology for Increased Sort Yield Using Automated Inspection," SPIE Proc., Vol. 921, 1988.
13. S. Strathman and S. Lotz, "Automated Inspection as Part of a Defect Reduction Program in an ASIC Manufacturing Environment," SPIE Proc., Vol. 1261. 1990.
14. L. Breaux and D. Kolar, "Automatic Defect Classification for Effective Yield Management," Solid State Technology, December 1996.
15. A. Shapiro, "Automatic Classification of Wafer Defects: Status and Industry Needs," IEE/CPMT Int'l. Electronics Manufacturing Technology Symposium, 1996.
16. B. Singh and S. Riley, "Automatic Defect Classification for Yield Management Strategies," Semiconductor International, March 1997.
17. J. Li, M. McIntyre, K. Lee and B. Worster, "Production Use of an Integrated Automatic Defect Classification (ADC) System Operating in a Laser Confocal/White Light Imaging Defect Review Station," IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 1996.
18. J. Bickley and A. Ohwada, "KLA 2710 Review Paper," KLA Instruments Corporation, February 19, 1993.
19. "The KLA 2700 Series SEMSpec Wafer Inspection System," KLA Instruments Technical Brief.
20. Fayyad, Piatetsky-Shapiro, Smyth and Uthurusamy, Advances in Knowledge Discovery and Data Mining, MTT Press, Cambridge, MA, 1996.
21. L. Connor, "Mining for Data," Communications Week, No. 596, February 12, 1996.
22. B. DePompa, "Data Mining - There's Gold in Databases," Information Week, No. 561, January 8th 1996.
23. H. Edelstein, "Technology How-To: Mining Data Warehouses, Information Week, No. 561, January 8th 1996.
24. th 1999.
25. M. Weider, "Q-Yield™ White Paper: Using Data Mining Software for Yield Analysis," Quadrillion Corporation. See also www.qualrillion.com
26. G. Scher, D. Eaton, B. Pernelius, J. Sorenson and J. Akers, "In-Line Statistical Process Control and Feedback for VLSI Integrated Circuit Manufacturing," IEEE Trans. Components, Hybrids and Mfg. Tech, Vol. 13, September 1990.
27. G. Scher, "Wafer Tracking Comes of Age," Semiconductor International, May 1991.
28. nd Annual International Symposium on Microlithography," Santa Clara, March 1997.
29. K. Tobin, S. Gleason, T. Karnowski and H. Sari-Sarraf, "An Image Paradigm for Semiconductor Defect Data Reduction," SPIE International Symposium on Microlithography, Santa Clara, March 1996. See also http://www-ismv.ic.oml.gov/projects/ssa.htm