CMOS and memories: From 100 nm to 10 nm!

Microelectronic Engineering

Volumn 46, Issue 1, 1999, Pages 3-6

  Tiwari, Sandip ^a   Solomon, Paul M ^a   Welser, J J ^a   Jones, E C ^a   McFeely, F R ^a   Cartier, E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC RESISTANCE; ELECTROSTATICS; GATES (TRANSISTOR); LEAKAGE CURRENTS; NONVOLATILE STORAGE; SEMICONDUCTOR DOPING;

GATE INSULATOR TUNNELING; STATIC RANDOM ACCESS MEMORY (SRAM);

MICROELECTRONICS;

EID: 0033130709     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(99)00004-0     Document Type: Article

References (7)

1. 1. F. Rana et al., Appl. Phys. Lett. 69 (1996) 1104.
2. 2. T. Sekigawa and Y. Hayashi, Sol. St. Electron. 27 (1984) 827
3. 3. D. J. Frank et al., Tech. Dig. of IEDM (1992) 553.
4. 4. I. C. Yang et al., Tech. Dig. of IEDM (1995) 877.
5. 5. H.-S. P. Wong et al., Tech. Dig. of IEDM (1997) 427
6. 6. C. T. Black and J. J. Welser, IBM Res. Rep. RC 21177.
7. 7. M. V. Fischetti and S. E. Laux, DAMOCLES.