Suppression of reverse-short-channel effect in sub-0.1μm n-MOSFETs with Sb S/D implantation

Electronics Letters

Volumn 35, Issue 6, 1999, Pages 508-509

  Tsuno, M ^a   Tanaka, M ^a   Koh, M ^b   Iwamoto, K ^a   Murakami, H ^a   Shibahara, K ^a   Mattausch, M M ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COMPUTER SIMULATION; EXTRAPOLATION; INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; OXIDATION; SEMICONDUCTING ANTIMONY; THRESHOLD VOLTAGE; VOLTAGE MEASUREMENT;

INTERSTITIAL CHARACTERISTICS; REVERSE SHORT CHANNEL EFFECT;

MOSFET DEVICES;

EID: 0033100843     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19990325     Document Type: Article

References (9)

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