Single-gate 0.15 and 0.12 μm CMOS with Co salicide technology

Solid-State Electronics

Volumn 43, Issue 3, 1999, Pages 543-546

  Yoshitomi, Takashi ^a   Saito, Masanobu ^a   Ohguro, Tatsuya ^a   Ono, Mizuki ^a   Momose, Hisayo Sasaki ^a   Morifuji, Eiji ^a   Morimoto, Toyota ^a   Katsumata, Yasuhiro ^a   Iwai, Hiroshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COBALT; MOSFET DEVICES; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS; SOLID STATE OSCILLATORS;

INVERTER RING-OSCILLATORS; SHORT CHANNEL EFFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 0033099835     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(98)00275-5     Document Type: Article

References (7)

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3. Lee KF, Yan RH, Jeon DY, Chin GM, Kim YO, Tennant DM, Razavi B, Lin HD, Wey YG, Westerwick EH, Morris MD, Jhonson RW, Liu TM, Tarsia M, Cerullo M, Swartz RG, Ourmazd A. Room temperature 0.1 μm CMOS technology with 11.8 ps gate delay. IEDM Tech Dig 1993;00:131-4.
4. 2 dual gate process. Symp on VLSI Tech Digest, 1995:9-10.
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6. Yoshitomi T, Saito M, Ohguro T, Ono M, Momose HS, Iwai H. A high performance 0.15 μm single gate CMOS technology. Extended Abstracts of the 1995 International Conference on Solid State Device and Materials, Osaka, 1995:222-224.
7. Saito M, Yoshitomi T, Hara H, Ono M, Akasaka Y, Nii H, Matsuda S, Momose HS, Katsumata Y, Ushiku Y, Iwai H. P-MOSFETs with ultra-shallow solid-phase-diffused drain structure produced by diffusion from BSG gate-sidewall. IEEE Trans Electr Dev 1993;40:2264-72.