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Volumn 48, Issue 3, 1999, Pages 331-344

A comparative analysis of cache designs for vector processing

Author keywords

Benchmarks; Cache memories; Memory hierarchy; Performance evaluation; Simulation; Vector processing

Indexed keywords

COMPUTER SELECTION AND EVALUATION; COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; GENERAL PURPOSE COMPUTERS; RESPONSE TIME (COMPUTER SYSTEMS); VECTORS;

EID: 0033099790     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.754999     Document Type: Review
Times cited : (4)

References (17)
  • 1
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    • D.H. Bailey, "Vector Computer Memory Bank Contention," IEEE Trans. Computers, vol. 36, no. 3, pp. 293-298, Mar. 1987.
    • (1987) IEEE Trans. Computers , vol.36 , Issue.3 , pp. 293-298
    • Bailey, D.H.1
  • 2
    • 0038835470 scopus 로고
    • Strategies for Cache and Local Memory Management by Global Program Transformation
    • D. Gannon, W. Jalby, and K. Gallivan, "Strategies for Cache and Local Memory Management by Global Program Transformation," Proc. Int'l Conf. Supercomputing, 1987.
    • (1987) Proc. Int'l Conf. Supercomputing
    • Gannon, D.1    Jalby, W.2    Gallivan, K.3
  • 5
    • 0024173488 scopus 로고
    • A Case for Direct-Mapped Caches
    • Dec.
    • M.D. Hill, "A Case for Direct-Mapped Caches," Computer, pp. 25-40, Dec. 1988.
    • (1988) Computer , pp. 25-40
    • Hill, M.D.1
  • 6
    • 0002030708 scopus 로고
    • The Perfect Club Benchmarks: Effective Performance Evaluation of Supercomputers
    • Fall
    • M. Berry et al., "The Perfect Club Benchmarks: Effective Performance Evaluation of Supercomputers," Int'l J. Supercomputer Applications, Fall 1989.
    • (1989) Int'l J. Supercomputer Applications
    • Berry, M.1
  • 11
    • 0025782109 scopus 로고
    • Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems
    • Jan.
    • D.T. Harper III, "Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems," IEEE Trans. Parallel and Distributed Systems, vol. 1, no. 1, Jan. 1991.
    • (1991) IEEE Trans. Parallel and Distributed Systems , vol.1 , Issue.1
    • Harper III, D.T.1
  • 13
    • 0026283224 scopus 로고
    • Measurement of Memory Access Contentions in Multiple Vector Processor Systems
    • Nov.
    • I.Y. Bucher and M.L. Simmons, "Measurement of Memory Access Contentions in Multiple Vector Processor Systems," Proc. Supercomputing '91, Nov. 1991.
    • (1991) Proc. Supercomputing '91
    • Bucher, I.Y.1    Simmons, M.L.2
  • 16
    • 0027885283 scopus 로고
    • Introducing a New Cache Design into Vector Computers
    • Dec.
    • Q. Yang, "Introducing a New Cache Design into Vector Computers," IEEE Trans. Computers, vol. 42, no. 12, Dec. 1993.
    • (1993) IEEE Trans. Computers , vol.42 , Issue.12
    • Yang, Q.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.