Computation of lower bounds for switching activity using decision theory

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 1, 1999, Pages 125-129

  Krishna, Vamsi ^b   Chandramouli, R ^b   Ranganathan, N ^a,b  

^a IEEE

^b University of South Florida   (United States)

Author keywords

CMOS circuits; Decision theory; Register transfer level; Switching activity

Indexed keywords

DECISION THEORY; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE MODELS;

REGISTER TRANSFER LEVEL;

CMOS INTEGRATED CIRCUITS;

EID: 0033099470     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.748209     Document Type: Article

References (11)

1. D. Marculescu, R. Marculescu, and M. Pedram, "Information theoretic measures for power analysis," IEEE Trans. Computer-Aided Design, vol. 15, pp. 599-610, June 1996.
2. F. Najm, "Toward a high level power estimation capability," IEEE Trans. Computer-Aided Design, vol. 15, pp. 588-598, June, 1996.
3. N. Shanbhag, "Lower bounds on power dissipation for DSP algorithms," in Proc. Int. Symp. Low-Power Design, 1996, pp. 43-48.
4. S. Ramprasad, N. Shanbhag, and I. N. Hajj, "Achievable bounds on signal transition activity," in Proc. ICCAD, 1997, pp. 126-129.
5. L. P. Yuan, C. C. Teng, and S. M. Kang, "Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques," in Proc. Int. Symp. Low-Power Design, 1996, pp. 73-78.
6. F. Najm and M. Y. Zhang, "Extreme delay sensitivity and the worst case switching activity in VLSI circuits," in Proc. IEEE/ACM Design Automation Conf., 1995, pp. 623-627.
7. Z. Chen, K. Roy, and T. L. Chou, "Power sensitivity - A new method to estimate power dissipation considering uncertain specifications of primary inputs," in Proc. ICCAD, 1997, pp. 40-44.
8. R. Marculescu, D. Marculescu, and M. Pedram, "Logic level power estimation considering spatiotemporal correlations," in Proc. Int. Conf. Computer-Aided Design, 1994, pp. 294-299.
9. J. O. Berger, Statistical Decision Theory and Bayesian Analysis. Berlin, Germany: Springer-Verlag, 1985.
10. T. Cover and P. Hart, "Nearest neighbor pattern classification," IEEE Trans. Inform. Theory, vol. IT-13, pp. 21-27, Jan. 1967.
11. E. M. Sentovich et al., "Sequential circuit design using synthesis and optimization," in Proc. ICCD, 1992, pp. 328-333.