An investigation of PWB layout by genetic algorithms to maximize fatigue life

Journal of Electronic Packaging, Transactions of the ASME

Volumn 121, Issue 1, 1999, Pages 31-36

  Scholand, A J ^a   Fulton, R E ^a   Bras, B ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; EPOXY RESINS; FATIGUE OF MATERIALS; FINITE ELEMENT METHOD; GENETIC ALGORITHMS; PRINTED CIRCUIT DESIGN; THERMAL EFFECTS;

SURFACE MOUNTED LEADLESS CHIP CARRIERS;

PRINTED CIRCUIT BOARDS;

EID: 0033098884     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.2792658     Document Type: Article

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