Peephole optimization of asynchronous macromodule networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 1, 1999, Pages 30-37

  Gopalakrishnan, Ganesh ^a,b   Kudva, Prabhakar ^a,c   Brunvand, Erik ^b  

^a IEEE

^b University of Utah   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Asynchronous circuits; Burst mode controllers; Delay insensitivity; Macromodules; Peephole optimization; Resynthesis

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

ASYNCHRONOUS MACROMODULE NETWORKS; BURST-MODE CONTROLLERS;

VLSI CIRCUITS;

EID: 0033097352     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.748198     Document Type: Article

References (31)

1. Y. N. Patt, S. J. Patel, M. Evers, D. H. Friendly, and J. Stark, "One billion transistors, one uniprocessor, one chip," IEEE Trans. Comput., vol. 30, pp. 51-58, Sept. 1997.
2. G. A. Pratt and J. Nguyen, "Distributed synchronous clocking," IEEE Trans. Parallel Distrib. Syst., vol. 6, pp. 314-328, Mar. 1995.
3. J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," Digital Tech. J., vol. 9, no. 1, pp. 49-62, 1997.
4. A. Davis, B. Coates, and K. Stevens, "The post office experience: Designing a large asynchronous chip," in Proc. Hawaii Int. Conf. Syst. Sci., vol. I. Piscataway, NJ: IEEE Comput. Soc. Press, 1993, pp. 409-418.
5. A. Marshall, B. Coates, and P. Siegel, "Designing an asynchronous communications chip," IEEE Design & Test of Computers, vol. 11, no. 2, pp. 8-21, 1994.
6. K. van Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken, F. Schalij, and R. van de Wiel, "A single-rail re-implementation of a DCC error detector using a generic standard-cell library," in Asynchronous Design Methodologies. Piscataway, NJ: IEEE Comput. Soc. Press, 1995, pp. 72-79.
7. A. Davis and S. M. Nowick, "Asynchronous circuit design: Motivation, background, & methods," in Asynchronous Digital Circuit Design, C. J. van Rijsbergen, Ed.. Berlin, Germany: Springer-Verlag, 1995, pp. 1-49.
8. J. Haans, K. van Berkel, A. Peeters, and F. Schalij, "Asynchronous multipliers as combinational handshake circuits," in Proc. IFIP Working Conf. Asynchronous Design Methods, Manchester, U.K., Mar. 31-Apr. 2, 1993.
9. E. Brunvand and R. F. Sproull, "Translating concurrent programs into delay-insensitive circuits," in Int. Conf. Comput. Design, Nov. 1989, pp. 262-265.
10. V. Akella and G. Gopalakrishnan, "SHILPA: A high-level synthesis system for self-timed circuits," in Int. Conf. Computer-Aided Design, ICCAD'92, Nov. 1992, pp. 587-591.
11. S. M. Ornstein, M. J. Stucki, and W. A. Clark, "A functional description of macromodules," in Spring Joint Computer Conf, AFIPS, 1967.
12. I. Sutherland, "Micropipelines," Commun. ACM, June 1989.
13. E. Brunvand, "A cell set for self-timed design using actel FP-GA's," Dept. Comput. Sci., Univ. Utah, Salt Lake City, UT, Tech. Rep. 91-013, 1991.
14. E. Brunvand, "Using FPGA's to implement self-timed systems," J. VLSI Signal Processing, (Special Issue on Field Programmable Logic, ) vol. 6, 1993.
15. J. T. Udding, "A formal model for defining and classifying delay-insensitive circuits and systems," Distributed Computing, no. 1, pp. 197-204, 1986.
16. E. Brunvand, "Translating concurrent communicating programs into asynchronous circuits," Ph.D. dissertation, Carnegie-Mellon Univ. Pittsburgh, PA, 1991.
17. K. van Berkel, "Handshake circuits: An intermediary between communicating processes and VLSI," Ph.D. dissertation, Philips Res. Lab., Eindhoven, The Netherlands, 1992.
18. A. Davis, B. Coates, and K. Stevens, "The post office experience: Designing a large asynchronous chip," T. N. Mudge, V. Milutinovic, and L. Hunter, Eds., in Proc. 26th Annu. Hawaiian Int. Conf. Syst. Sci., vol. 1, Jan. 1993, pp. 409-418.
19. S. Nowick, "Automatic synthesis of burst-mode asynchronous controllers," Ph.D. dissertation, Dept. Comput. Sci., Stanford Univ., Stanford, CA, 1993.
20. S. M. Nowick, K. Y. Yun, and D. L. Dill, "Practical asynchronous controller design," in Proc. Int. Conf. Comput. Design, Oct. 1992, pp. 341-345.
21. K. Y. Yun, D. L. Dill, and S. M. Nowick, "Synthesis of 3d asynchronous state machines," in Proc. Int. Conf. Comput. Design, Oct. 1992, pp. 346-350.
22. S. Nowick, M. Dean, D. Dill, and M. Horowitz, "The design of a high-performance cache controller: A case study in asynchronous synthesis," T. N. Mudge, V. Milutinovic, and L. Hunter, Eds., in Proc. 26th Annu. Hawaiian Int. Conf. Syst. Sci., vol. 1, Jan. 1993, pp. 419-427.
23. G. Gopalakrishnan, N. Michell, E. Brunvand, and S. M. Nowick, "A correctness criterion for asynchronous circuit verification and optimization," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1309-1318, Nov. 1994.
24. A. J. Martin, "Programming in VLSI: From communicating processes to delay-insensitive circuits," in UT Year of Programming Institute on Cocurrent Programming, C. A. R. Hoare, Ed. Reading, MA: Addison-Wesley, 1989.
25. D. L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits (An ACM Distinguished Dissertation). Cambridge, MA: MIT Press, 1989.
26. S. H. Unger, Asynchronous Sequential Switching Circuits. New York: Wiley, 1969.
27. R. F. Sproull and I. E. Sutherland, Asynchronous Systems, Vol. I: Introduction. Palo Alto, CA: Sutherland, Sproull and Associates, 1986
28. D. L. Dill, S. M. Nowick, and R. F. Sproull, "Specification and automatic verification of self-timed queues," Formal Methods in Syst. Design, vol. 1, no. 1, pp. 29-62, July 1992.
29. E. Sternheim, R. Singh, and Y. Trivedi, Digital Design with Verilog HDL. Cupertino, CA: Automata 1990.
30. P. Kudva, G. Gopalakrishnan, and H. Jacobson, "A technique for synthesizing distributed burst-mode circuits," in Proc. 33th ACM/IEEE Design Automation Conf., Las Vegas, NV, June 1996, pp. 67-70.
31. S. Burns and A. Martin, "Performance analysis and optimization of asynchronous circuits," in Advanced Res. VLSI: Proc. 1991 Univ. California Santa Cruz Conf., C. Sequin, Ed. Cambridge, MA: MIT Press, 1991, pp. 71-86.