An architecture of a matrix-vector multiplier dedicated to video decoding and three-dimensional computer graphics

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 9, Issue 2, 1999, Pages 306-314

  Fujishima, Hideyuki ^a,b,c   Takemoto, Yusuke ^a,b   Onoye, Takao ^a,b   Shirakawa, Isao ^a,b  

^a IEEE   (Japan)

^b OSAKA UNIVERSITY   (Japan)

^c Kyushu Matsushita Electric Co Ltd   (Japan)

Author keywords

Geometrical transformation; Inverse discrete cosine transform (IDCT); Media processor; MPEG 4

Indexed keywords

COMPUTATIONAL GEOMETRY; COSINE TRANSFORMS; DECODING; IMAGE CODING; IMAGE COMPRESSION; INVERSE PROBLEMS; MATRIX ALGEBRA; ONE DIMENSIONAL; STANDARDS; THREE DIMENSIONAL COMPUTER GRAPHICS; VECTORS;

INVERSE DISCRETE COSINE TRANSFORM; MATRIX VECTOR MULTIPLIER; NATURAL SYNTHETIC VIDEO DECODING; VIDEO DECODING;

MULTIPLYING CIRCUITS;

EID: 0033097093     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.752097     Document Type: Article

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