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Volumn 86, Issue 2, 1999, Pages 189-205

Current-mode programmable synapse circuits for analogue ULSI neural networks

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; ULSI CIRCUITS;

EID: 0033079718     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/002072199133571     Document Type: Article
Times cited : (5)

References (27)
  • 1
    • 0344967072 scopus 로고
    • A novel linear resistor utilizing MOS transistors with identical sizes and one controlling voltage
    • Al-Ruwaihi, K. M., and Noras, J. M., 1994, A novel linear resistor utilizing MOS transistors with identical sizes and one controlling voltage. International Journal of Electronics, 76, 1083-1098.
    • (1994) International Journal of Electronics , vol.76 , pp. 1083-1098
    • Al-Ruwaihi, K.M.1    Noras, J.M.2
  • 2
    • 0029250589 scopus 로고
    • Programmable CMOS current comparator circuit for analogue VLSI neural networks utilizing identical small-dimension MOS transistors
    • Al-Ruwaihi, K. M., and Noras, J. M., 1995, Programmable CMOS current comparator circuit for analogue VLSI neural networks utilizing identical small-dimension MOS transistors. International Journal of Electronics, 78, 347-358.
    • (1995) International Journal of Electronics , vol.78 , pp. 347-358
    • Al-Ruwaihi, K.M.1    Noras, J.M.2
  • 5
    • 0025414349 scopus 로고
    • Programmable current-mode neural network for implementation in analogue MOS VLSI
    • Borgstrom, T H., Ismail, M., and Bibyk, S. B., 1990, Programmable current-mode neural network for implementation in analogue MOS VLSI. IEE Proceedings—G, 137, 175-184.
    • (1990) IEE Proceedings—G , vol.137 , pp. 175-184
    • Borgstrom, T.H.1    Ismail, M.2    Bibyk, S.B.3
  • 6
    • 0025522186 scopus 로고
    • Challenges to manufacturing submicron, ultra-large scale integrated circuits
    • Fair, R. B., 1990, Challenges to manufacturing submicron, ultra-large scale integrated circuits. Proceedings of the IEEE, 78, 1687-1705.
    • (1990) Proceedings of the IEEE , vol.78 , pp. 1687-1705
    • Fair, R.B.1
  • 11
    • 0025445432 scopus 로고
    • Artificial neural networks using MOS analog multipliers
    • Hollis, P.W., and Paulos, J. J., 1990, Artificial neural networks using MOS analog multipliers, IEEE Journal of Solid-State Circuits, 25, 849-855.
    • (1990) IEEE Journal of Solid-State Circuits , vol.25 , pp. 849-855
    • Hollis, P.W.1    Paulos, J.J.2
  • 13
    • 0027590094 scopus 로고
    • An analog CMOS chip set for neural networks with arbitrary topologies
    • Lansner, J. A., and LehMAnn, T, 1993, An analog CMOS chip set for neural networks with arbitrary topologies. IEEE Transactions on Neural Networks, 4, 441-444.
    • (1993) IEEE Transactions on Neural Networks , vol.4 , pp. 441-444
    • Lansner, J.A.1    Lehmann, T.2
  • 14
    • 0026925756 scopus 로고
    • General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons
    • Lee, B., and Sheu, B., 1992, General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons. IEEE Journal of Solid-State Circuits, 27, 1299-1303.
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , pp. 1299-1303
    • Lee, B.1    Sheu, B.2
  • 16
    • 0009491732 scopus 로고
    • Deep-submicron CMOS warms up to high-speed logic
    • November
    • Masaki, A., 1992, Deep-submicron CMOS warms up to high-speed logic, Circuits and Devices Magazine, November, 18-24.
    • (1992) Circuits and Devices Magazine , pp. 18-24
    • Masaki, A.1
  • 17
    • 0026852420 scopus 로고
    • Limitations, innovations, and challenges of circuits and devices into a half micrometer and beyond
    • Nagata, M., 1992, Limitations, innovations, and challenges of circuits and devices into a half micrometer and beyond. IEEE Journal of Solid-State Circuits, 27, 465-472.
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , pp. 465-472
    • Nagata, M.1
  • 20
    • 0028446161 scopus 로고
    • A Four-quadrant CMOS analog multiplier for analog neural networks
    • Saxena, N., and Clark, J., 1994, A Four-quadrant CMOS analog multiplier for analog neural networks. IEEE Journal of Solid-State Circuits, 29, 746-749.
    • (1994) IEEE Journal of Solid-State Circuits , vol.29 , pp. 746-749
    • Saxena, N.1    Clark, J.2
  • 22
    • 0029359665 scopus 로고
    • A neuron-MOS neural network using self-learning-compatible synapse circuits
    • Shibata, T, Kosaka, H., Ishii, H., and Ohmi, T, 1995, A neuron-MOS neural network using self-learning-compatible synapse circuits. IEEE Journal of Solid-State Circuits, 30, 913-922.
    • (1995) IEEE Journal of Solid-State Circuits , vol.30 , pp. 913-922
    • Shibata, T.1    Kosaka, H.2    Ishii, H.3    Ohmi, T.4
  • 24
    • 0027242785 scopus 로고
    • Analog neural network building blocks based on current mode subthreshold operation
    • Chicago, USA
    • Song, L., Elmasry, M. I., and VAnnelli, A., 1993, Analog neural network building blocks based on current mode subthreshold operation, Chicago, USA. In IEEE International Symposium on Circuits and Systems, pp. 2462-2465.
    • (1993) IEEE International Symposium on Circuits and Systems , pp. 2462-2465
    • Song, L.1    Elmasry, M.I.2    Vannelli, A.3
  • 26
    • 0023454091 scopus 로고
    • Analogue circuits for variable-synapse electronic neural networks
    • Tsividis, Y, and Satyanaryana, S., 1987, Analogue circuits for variable-synapse electronic neural networks. Electronics Letters, 23, 1313-1314.
    • (1987) Electronics Letters , vol.23 , pp. 1313-1314
    • Tsividis, Y.1    Satyanaryana, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.