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Volumn 34, Issue 2, 1999, Pages 219-226

Highly Integrated InP HBT Optical Receivers

Author keywords

Heterojunction bipolar transistor; Indium phosphide; Optical receiver; Optoelectronic integrated circuit

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; OPTOELECTRONIC DEVICES; PHOTODIODES; SEMICONDUCTING INDIUM PHOSPHIDE;

EID: 0033079311     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.743780     Document Type: Article
Times cited : (13)

References (15)
  • 2
    • 0028549917 scopus 로고
    • 23 GHz bandwidth monolithic photoreceiver compatible with InP/InGaAs double heterojunction bipolar transistor fabrication process
    • Nov.
    • E. Sano, M. Yoneyama, S. Yamahata, and Y. Matsuoka, "23 GHz bandwidth monolithic photoreceiver compatible with InP/InGaAs double heterojunction bipolar transistor fabrication process," Electron. Lett., vol. 30, no. 24, pp. 2064-2065, Nov. 1994.
    • (1994) Electron. Lett. , vol.30 , Issue.24 , pp. 2064-2065
    • Sano, E.1    Yoneyama, M.2    Yamahata, S.3    Matsuoka, Y.4
  • 6
    • 0030393351 scopus 로고    scopus 로고
    • A review of recent progress in InP-based optoelectronic integrated circuit receiver front-ends
    • R. Walden, "A review of recent progress in InP-based optoelectronic integrated circuit receiver front-ends," in Tech. Dig. 1996 GaAs IC Symp., 1996, pp. 255-256.
    • (1996) Tech. Dig. 1996 GaAs IC Symp. , pp. 255-256
    • Walden, R.1
  • 8
    • 0031144921 scopus 로고    scopus 로고
    • 16 × 16 two-dimensional optoelectronic integrated receiver array for highly parallel interprocessor networks
    • N. Yano, S. Sawada, K. Doguchi, T. Kato, and G. Sasaki, "16 × 16 two-dimensional optoelectronic integrated receiver array for highly parallel interprocessor networks," IEICE Trans. Electron., vol. E80-C, no. 5, pp. 689-694, 1997.
    • (1997) IEICE Trans. Electron. , vol.E80-C , Issue.5 , pp. 689-694
    • Yano, N.1    Sawada, S.2    Doguchi, K.3    Kato, T.4    Sasaki, G.5
  • 11
    • 0030270725 scopus 로고    scopus 로고
    • A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor
    • Oct.
    • F. Sato, H. Tezuka, M. Soda, T. Hashimoto, T. Suzaki, T. Tatsumi, T. Morikawa, and T. Tashiro, "A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor," IEEE J. Solid-State Circuits, vol. 31, pp. 1451-1457, Oct. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 1451-1457
    • Sato, F.1    Tezuka, H.2    Soda, M.3    Hashimoto, T.4    Suzaki, T.5    Tatsumi, T.6    Morikawa, T.7    Tashiro, T.8
  • 15
    • 0027855292 scopus 로고
    • A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technology
    • Dec.
    • M. Soyuer, "A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technology," IEEE J. Solid-State Circuits, vol. 28, pp. 1310-1313, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 1310-1313
    • Soyuer, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.