Yield modeling based on in-line scanner defect sizing and a circuit's critical area

IEEE Transactions on Semiconductor Manufacturing

Volumn 12, Issue 1, 1999, Pages 26-35

  Milor, Linda S ^a,b  

^a IEEE   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Integrated circuit layout; Integrated circuit manufacture; Measurement errors; Size measurement; Yield estimation

Indexed keywords

DEFECTS; ELECTRIC NETWORK ANALYSIS; INSPECTION; MEASUREMENT ERRORS; PARAMETER ESTIMATION; SIZE DETERMINATION;

CIRCUITS CRITICAL AREA; IN-LINE SCANNER DEFECT SIZING; YIELD MODELING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033079061     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.744517     Document Type: Article

References (5)

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2. H. T. Heineken and W. Maly, "Manufacturability analysis environment - MAPEX," in Proc. CICC, 1994, pp. 309-312.
3. W. Maly and J. Deszczka, "Yield estimation mode for VLSI artwork evaluations," Electron. Lett., vol. 19, no. 6, pp. 226-227, Mar. 1983.
4. J. A. Cunningham, "The use and evaluation of yield models in integrated circuit manufacturing," IEEE Trans. Semiconduct. Manufact., vol. 3, pp. 60-71, May 1990.
5. R. K. Nurani et al., "In-line yield prediction methodologies using patterned wafer inspection information," in Proc. ISSM, 1996, pp. 243-248.