An executable specification and verifier for relaxed memory order

IEEE Transactions on Computers

Volumn 48, Issue 2, 1999, Pages 227-235

  Park, Seungjoon ^b   Dill, David L ^a,c  

^a IEEE   (United States)

^b NASA AMES RESEARCH CENTER   (United States)

^c Stanford University   (United States)

Author keywords

Automatic verification; Executable specification; Formal method; Memory models; Multiprocessors

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FORMAL LANGUAGES; MULTIPROCESSING SYSTEMS;

EXECUTABLE SPECIFICATIONS; RELAXED MEMORY ORDER;

DATA STORAGE EQUIPMENT;

EID: 0033076216     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.752664     Document Type: Article

References (22)

1. W.W. Collier, Reasoning About Parallel Architectures. Prentice Hall, 1992.
2. J. Protić, M. Tomašević, and V. Milutinović, eds., Distributed Shared Memory: Concepts and Systems. IEEE CS, 1998,
3. L Lamport, "How to Make a Multiprocessor Computer that Correctly Executes Multiprocessor Programs," IEEE Trans. Computers, vol. 28, no. 9, pp. 690-691, Sept. 1979.
4. J.R. Goodman, "Cache Consistency and Sequential Consistency," Technical Report 61, SCI Committee, Mar. 1989.
5. K. Gharachorloo, D. Lenoski, J. Laudon, P. Gibbons, A. Gupta, and J. Hennessy, "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors," Proc. 17th Ann. Int'l Symp. Computer Architecture, pp. 15-26, May 1990.
6. K. Gharachorloo, "Memory Consistency Models for Shared-Memory Multiprocessors," PhD thesis, Stanford Univ., 1996.
7. SPARC International, The SPARC Architecture Manual Version 8. Prentice Hall, 1992.
8. P.S. Sindhu, J.-M. Frailong, and M. Cekleov, "Formal Specification of Memory Models," Technical Report CSL-91-11, Xerox Palo Alto Research Center, Dec. 1991.
9. M. Dubois, C. Scheurich, and F. Briggs, "Memory Access Buffering in Multiprocessors," Proc. 13th Ann. Int'l Symp. Computer Architecture, pp. 434-442, June 1986.
10. S. Adve and M. Hill, "Weak Ordering - New Definition and Some Implications," Proc. 17th Ann. Int'l Symp. Computer Architecture, pp. 2-14, 1990.
11. D. Weaver and T. Germond, eds., The SPARC Architecture Manual Version 9. Prentice Hall, 1994.
12. R. Sites and R. Witek, eds., Alpha AXP Architecture Reference Manual, second ed.. Digital Press, 1995.
13. C. May, E. Silha, R. Simpson, and H. Warren, eds., The PowerPC Architecture: A Specification for a New Family of RISC Processors. Morgan Kaufmann, 1994.
14. S. Adve and M. Hill, "Implementing Sequential Consistency in Cache-Based Systems," Proc. Ninth Int'l Symp. Parallel Processing, pp. 47-50, Aug. 1990.
15. C. Scheurich and M. Dubois, "Correct Memory Operation of Cache-Based Multiprocessors," Proc. 14th Ann. Int'l Symp. Computer Architecture, pp. 234-243, 1987.
16. D.L. Dill, "The Murφ Verification System," Proc. Computer Aided Verification, Eighth Int'l Conf., CAV '96, pp. 390-393. Springer-Verlag, July 1996.
17. S. Owre, J. Rushby, N. Shankar, and F. von Henke, "Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS," IEEE Trans. Software Eng., vol. 21, no. 2, pp. 107-125, Feb. 1995.
18. K. Gharachorloo, S. Adve, A. Gupta, J. Hennessy, and M. Hill, "Programming for Different Memory Consistency Models," J. Parallel and Distributed Computing, vol. 15, no. 4, pp. 399-407, Aug. 1992.
19. P. Gibbons, M. Merritt, and K. Gharachorloo, "Proving Sequential Consistency of High-Performance Shared Memories," Proc. Third ACM Symp. Parallel Algorithms and Architectures, pp. 292-303, July 1991.
20. N. Lynch, "I/O Automata: A Model for Discrete Event Systems," Proc. 22nd Ann. Conf. Information Science and Systems, Princeton Univ., Mar. 1988.
21. D.L. Dill, S. Park, and A. Nowatzyk, "Formal Specification of Abstract Memory Models," Research on Integrated Systems: Proc. 1993 Symp., pp. 38-52. MIT Press, Mar. 1993.
22. M. Ben-Ari, Principles of Concurrent and Distributed Programming. Prentice Hall, 1990.