Implementing new dispatching rules at sgs-thomson microelectronics

Production Planning and Control

Volumn 10, Issue 1, 1999, Pages 97-106

  Cigolini, Roberto ^a   Comi, Alessandro ^b   Micheletti, Armando ^b   Perona, Marco ^a   Portioli, Alberto ^a  

^a POLITECNICO DI MILANO   (Italy)

^b SGS Thomson Microelectronics   (Switzerland)

Author keywords

Dispatching; Semiconductor Manufacturing; Wafer Fab

Indexed keywords

COMPUTER SIMULATION; CONSTRAINT THEORY; DISTRIBUTION OF GOODS; INTEGRATED CIRCUIT MANUFACTURE; PROCESS CONTROL; SCHEDULING; STRATEGIC PLANNING; VLSI CIRCUITS;

SHORT TERM PRODUCTION PLANNING AND CONTROL;

JUST IN TIME PRODUCTION;

EID: 0032761113     PISSN: 09537287     EISSN: 13665871     Source Type: Journal    
DOI: 10.1080/095372899233479     Document Type: Article

References (26)

1. Baker, K. R, 1974, Introduction to Sequencing and Scheduling (New York: J ohn Wiley)
2. Blackstone, J. H., Phillips, D.T., and Hogg, G. L., 1982, A state-of-the-art survey of dispatching rules for manufacturing job shop operations. International J ournal of Production Research, 20, 27-45.
3. cam group, 1991, WorkStream: CAM System; Handbook. (SGS-Thomson Microelectronics Internal Publication).
4. Cigolini, R., Perona, M., Pdrtidli, A, Turco, F., and Zambelli, T., 1996, Comparison of different dispatching rules in VLSI semiconductor manufacturing: a simulation approach. In P roceedings of the 8th European Simulation Symposium, (24-26, October, Genoa, Italy), vol. 1, pp. 343-347.
5. Glassey, C R., and Resende, M G.C., 1988, Closed-loop job release control for VLSI circuit manufacturing. ieee T ransaction on Semiconductor M anufacturing, 1, 36-46.
6. Graves, S. C, 1981, A review of production scheduling. Operations Research, 29, 646-675
7. Gurnani, H., Anupindi, R., and Akella, R., 1992, Control of batch processing systems in semiconductor wafer fabrication facilities. IEEE T ransactions on Semiconductor M anufacturing, 5, 319- 327.
8. Hashiivdto, C., Takeda, T., Tazawa, S., and Sakurai, T., 1993, Practical scheduling and line optimisation technology for ASIC manufacturing lines. IEEE Transactions on Components, Hybrids and M anufacturing T echnology, 16, 407-411.
9. Kumar, P. R, 1994, Scheduling manufacturing systems of reentrant lines. In: David D. Yao (ed.) Stochastic M odelling and Analysis of M anufacturing Systems, pp. 325-360 (New York: Springer Verlag).
10. Lee, C-Y, Uzsdy, R., and Martin-Vega L. A, 1992, Efficient algorithms for scheduling semiconductor burn-in operations. Operations Research, 40, 764-775
11. McCutchen, T., and Lee, C.-Y., 1995, An analysis of dispatching rules in a semiconductor wafer fabrication environment. J ournal of Electronics M anufacturing, 5, 165-174.
12. Mitra, A, Cox, J.F., and Kellizy A, 1981, Statistical aspects in a simulation study. Computer and Industrial E ngineering, 5, 195-204.
13. MONTGOMERY, D. C., 1984, Design and Analysis of E xperiments (New York: John Wiley).
14. Montgomery, D. C., 1985, Introduction to Statistical Quality Control (New York: J ohn Wiley).
15. Motta, A., 1994a, Diffusion Protect Training Handbook. (SGS-Thomson Microelectronics Internal Publication).
16. Motta, A., 1994b, Ion Implanter N V 620 and NV 10-160 T raining Handbook (SGS-Thomson Microelectronics Internal Publication).
17. Motta, A., 1994c, PooL Top Quality (SGS-Thomson Microelectronics Internal Publication).
18. Panwalkar, S. S., and Iskander, W, 1977, A survey of scheduling rules. O perations Research, 25, 45- 63.
19. Pegden, C D, and Shannon, R., 1990, Introduction to Simulation using sim an (New York: McGraw-Hill).
20. Schildt, H., 1989, Turbo c (New York: McGraw-Hill).
21. Uzsdy, R., 1994, Scheduling a single batch processing machine with non-identical job size. International J ournal of Production R esearch. 32, 1615-1635.
22. Uzsdy, R., Lee, C.-Y, and Martin-Vega, L. A., 1992, A review of production planning and scheduling models in the semiconductor industry. part I: system characteristics, performance evaluation and production planning. ieee T ransactions, 24, 47- 60.
23. Uzsdy, R., Lee, C.-Y., and Martin-Vega, L. A., 1994, A review of production planning and scheduling models in the semiconductor industry. part II: shop-floor control. IEEE Transactions, 26, 44-55.
24. Vepsalainen, A. P. J., and Morton, T. E., 1988, Improving Local Priority Rules with Global Lead-time Estimates (Amsterdam: Elsevier Science).
25. Wein, L. M., 1988, Scheduling semiconductor wafer fabrication. IEEE T ransaction on Semiconductor M anufacturing, 1, 115-130
26. Zambelli, T. A., 1996, A new approach to the re-entrant lines scheduling problem in the semiconductor manufacturing. M aster D egree T hesis. Dipartimento di Economia e Produzione, Politecnico di Milano (in Italian).