Multi-valued logic synthesis

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1999, Pages 196-205

  Brayton, Robert K ^a   Khatri, Sunil P ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; MANY VALUED LOGICS; OPTIMIZATION;

BINARY-VALUED LOGIC;

LOGIC DESIGN;

EID: 0032735597     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icvd.1999.745148     Document Type: Conference Paper

References (10)