Efficient techniques for reducing IDDQ observation time for sequential circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1999, Pages 72-77

  Higami, Yoshinobu ^a   Saluja, Kewal K ^a   Kinoshita, Kozo ^a  

^a EHIME UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; ELECTRIC CURRENT MEASUREMENT; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING; VECTORS;

QUIESCENT CURRENT TESTING;

SEQUENTIAL CIRCUITS;

EID: 0032735596     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icvd.1999.745127     Document Type: Conference Paper

References (7)