vMOS-based sorters for multiplier implementations

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1999, Pages

  Rodriguez Villegas, E ^a   Avedillo, M J ^a   Quintana, J M ^a   Huertas, G ^a   Rueda, A ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; SIGNAL THEORY; THRESHOLD LOGIC;

BINARY SORTERS; SORTING NETWORKS;

MULTIPLYING CIRCUITS;

EID: 0032715921     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)