Towards synthetic benchmark circuits for evaluating timing-driven CAD tools

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 1999, Pages 60-66

  Stroobandt, Dirk ^a   Verplaetse, Peter ^a   Van Campenhout, Jan ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LOGIC DEVICES;

SYNTHETIC BENCHMARK CIRCUITS; TIMING-DRIVEN COMPUTER AIDED DESIGN TOOLS;

VLSI CIRCUITS;

EID: 0032689922     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/299996.300023     Document Type: Article

References (16)