Reducing average number of turbo decoding iterations

Electronics Letters

Volumn 35, Issue 9, 1999, Pages 701-702

  Shibutani, A ^a   Suda, H ^a   Adachi, F ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; ERROR CORRECTION; ERROR DETECTION; ITERATIVE METHODS; RAYLEIGH FADING;

CYCLIC REDUNDANCY CHECK (CRC) ERROR DETECTION; TURBO DECODERS;

DECODING;

EID: 0032689527     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19990470     Document Type: Article

References (6)

1. ADACHI, F., SAWAHASHI, M., and SUDA, H.: 'Wideband DS-CDMA for next generation mobile communications', IEEE Commun. Mag., 1998, 36, pp. 56-69
2. BERROU, C., GLAVIEUX, A., and THITIMAJSHIMA, P.: 'Near Shannon limit error-correcting coding and decoding: turbo-codes'. Proc. IEEE ICC'93, May Geneva, 1993, pp. 1064-1070
3. FUJIWARA, A., SUDA, H., and ADACHI, F.: 'Turbo codes application to DS-CDMA mobile radio', IEICE Trans., 1998, E81-A. pp. 2269-2273
4. SHIBUTANI, A., SUDA, H., and ADACHI, F.: 'Multi-stage interleaver for turbo codes in DS-CDMA mobile radio'. Proc. IEEE APCC/ ICCS'98, Singapore, November 1998, pp. 391-395
5. 'Procedure for evaluation of transmission technologies for FPLMTS'. ITU-R TG8-1, 8-1/TEMP/233-E, September 1995
6. SEO, S., DOHI, T., and ADACHI, F.: 'SIR-based transmit power control of reverse link for coherent DS-CDMA mobile radio', IEICE Trans., 1998, E81-B, pp. 1508-1516