MOS noise performance under impedance matching constraints

Electronics Letters

Volumn 35, Issue 15, 1999, Pages 1278-1280

  Janssens, J ^a   Steyaert, H ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; IMPEDANCE MATCHING (ELECTRIC); OPTIMIZATION; THERMAL NOISE;

IMPEDANCE MATCHING CONSTRAINTS; MOS NOISE;

MOS DEVICES;

EID: 0032689477     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19990837     Document Type: Article

References (3)

1. LEE T.H.: 'The design of CMOS radio-frequency integrated circuits' (Cambridge University Press 1998), pp. 281-284
2. JANSSENS, J., and STEYAERT, M.: 'Optimum MOS power matching by exploiting non-quasistatic effect', Electron. Lett., 1999, 35, (8) pp. 672-673
3. TSIVIDIS, Y.P.: 'Operation and modelling of the MOS transistor' (McGraw-Hill, 1987), chap. 6, p. 399