An interface circuit for a Josephson-CMOS hybrid digital system

IEEE Transactions on Applied Superconductivity

Volumn 9, Issue 2 PART 3, 1999, Pages 3314-3317

  Suzuki, M ^a   Maezawa, M ^a   Takato, H ^a   Nakagawa, H ^a   Hirayama, F ^a   Kiryu, S ^a   Aoyagi, M ^a   Sekigawa, T ^a   Shqji, A ^a  

^a Electrotech Lab   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; DATA TRANSFER; ELECTRIC INVERTERS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; JOSEPHSON JUNCTION DEVICES; LOGIC GATES; SYNCHRONIZATION;

INTERFACE CIRCUIT; LATCHING LOGIC TECHNOLOGY; PARALLEL IN PARALLEL OUT CIRCUIT;

DIGITAL INTEGRATED CIRCUITS;

EID: 0032685234     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.783738     Document Type: Article

References (3)

1. H. Kroger and U. Ghoshal, "Can superconductive digital system compete with semiconductor systems?," IEEE Trans. Appl. Supercond, vol. 3, pp. 2307-2314, March 1993.
2. A. Shoji, "Josephson-MOS interface circuit technologies," in Extended Abstract of 16th Symposium on Future Electron Devices, FED-159, Tokyo, Oct." 1997, pp. 185-190.
3. S. Takada, H. Nakagawa. I. Kurosawa, M. Aoyagi, S. Kosaka, Y. Okada, and Y. Hamazaki, "A multichip superconducting microcomputer ETL-JC1," IEEE Trans, on Magn., vol. 27, pp. 2610-2617, 1991.