Layout dependent matching analysis of CMOS circuits

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E82-A, Issue 2, 1999, Pages 348-355

  Okada, Kenichi ^a   Onodera, Hidetoshi ^a   Tamaru, Keikichi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE MODELS;

LAYOUT MATCHING ANALYSIS; MICRO-LOADING EFFECT;

CMOS INTEGRATED CIRCUITS;

EID: 0032682997     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (11)