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Volumn 6, Issue , 1999, Pages 3517-3520
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New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTATIONAL COMPLEXITY;
FAST FOURIER TRANSFORMS;
MATRIX ALGEBRA;
SYSTOLIC ARRAYS;
VLSI CIRCUITS;
DISCRETE COSINE TRANSFORMS (DCT);
COSINE TRANSFORMS;
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EID: 0032681819
PISSN: 07367791
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Article |
Times cited : (2)
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References (6)
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