메뉴 건너뛰기




Volumn 15, Issue 2, 1999, Pages 12-22

Enhanced analog "yields" cost-effective systems-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER AIDED DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; CORRELATION METHODS; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MIXER CIRCUITS; MOS DEVICES; OPTIMIZATION; VLSI CIRCUITS;

EID: 0032676665     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.755472     Document Type: Article
Times cited : (12)

References (27)
  • 3
    • 0032257652 scopus 로고    scopus 로고
    • Statistical modeling and circuit simulation for design for manufacturing
    • San Francisco, CA, December
    • T. Smedes and P.G.A. Emonts, "Statistical modeling and circuit simulation for design for manufacturing," Proc. International Electron Devices Meeting, San Francisco, CA, December 1998.
    • (1998) Proc. International Electron Devices Meeting
    • Smedes, T.1    Emonts, P.G.A.2
  • 4
    • 0026256867 scopus 로고
    • Parametric Yield Optimization of CMOS Analog Circuits by Quadratic Statistical Circuit Performance Models
    • November
    • T.K. Yu, S.M. Kang, J. Sacks and W.J. Welch, "Parametric Yield Optimization of CMOS Analog Circuits by Quadratic Statistical Circuit Performance Models," Int. J. Circuit Theory Appl., vol. 19, pp. 579-592, November 1991.
    • (1991) Int. J. Circuit Theory Appl. , vol.19 , pp. 579-592
    • Yu, T.K.1    Kang, S.M.2    Sacks, J.3    Welch, W.J.4
  • 5
    • 0030142517 scopus 로고    scopus 로고
    • Statistical techniques for the computer-aided optimization of analog integrated circuits
    • May
    • C. Michael, H. Su, M. Ismail, A. Kankunnen and M. Valtonen, "Statistical techniques for the computer-aided optimization of analog integrated circuits," IEEE Trans. Circuits Syst. I, vol. 43, pp. 410-413, May 1996.
    • (1996) IEEE Trans. Circuits Syst. I , vol.43 , pp. 410-413
    • Michael, C.1    Su, H.2    Ismail, M.3    Kankunnen, A.4    Valtonen, M.5
  • 6
    • 0021586347 scopus 로고
    • Random error effects in matched MOS capacitors and current sources
    • December
    • J.-B. Shyu, G.C. Temes and F. Krummenacher, "Random error effects in matched MOS capacitors and current sources," IEEE J. Solid-State Circuits, vol. SC-19, pp. 948-955, December 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SC-19 , pp. 948-955
    • Shyu, J.-B.1    Temes, G.C.2    Krummenacher, F.3
  • 7
  • 8
    • 0022891057 scopus 로고
    • Characterization and modeling of mismatch in MOS transistors for precision analog design
    • December
    • K.R. Lakshmikumar, R.A. Hadaway and M.A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, December 1986.
    • (1986) IEEE J. Solid-State Circuits , vol.SC-21 , pp. 1057-1066
    • Lakshmikumar, K.R.1    Hadaway, R.A.2    Copeland, M.A.3
  • 11
    • 0345611934 scopus 로고    scopus 로고
    • Statistical Design and Optimization for High-Yield BiCMOS Analog Circuits, chapter 17
    • G.A. Machado (editor). London: The Institute of Electrical Engineers (IEE)
    • H.Y. To, C.C. Hung, H. Su, and M. Ismail, Statistical Design and Optimization for High-Yield BiCMOS Analog Circuits, chapter 17 in Low-Power HF Microelectronics, G.A. Machado (editor). London: The Institute of Electrical Engineers (IEE), 1996.
    • (1996) Low-Power HF Microelectronics
    • To, H.Y.1    Hung, C.C.2    Su, H.3    Ismail, M.4
  • 12
    • 0030193132 scopus 로고    scopus 로고
    • Mismatch modeling and characterization of bipolar transistors for statistical CAD
    • July
    • H.Y. To and M. Ismail, "Mismatch modeling and characterization of bipolar transistors for statistical CAD," IEEE Trans. Circuits Syst. I, vol. 43, pp. 608-610, July 1996.
    • (1996) IEEE Trans. Circuits Syst. I , vol.43 , pp. 608-610
    • To, H.Y.1    Ismail, M.2
  • 13
    • 0027297610 scopus 로고
    • Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits
    • C. Abel, C. Michael, M. Ismail, C.S. Teng and R. Lahri, "Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits," Int. Symp. Circuits Syst., vol.3, pp. 1401-1404, 1993
    • (1993) Int. Symp. Circuits Syst. , vol.3 , pp. 1401-1404
    • Abel, C.1    Michael, C.2    Ismail, M.3    Teng, C.S.4    Lahri, R.5
  • 18
    • 0026819378 scopus 로고
    • Statistical modeling of device mismatch for analog MOS integrated circuits
    • February
    • C. Michael and M. Ismail, "Statistical modeling of device mismatch for analog MOS integrated circuits," IEEE J. Solid-State Circuits, vol. SC-27, pp. 154-166, February 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.SC-27 , pp. 154-166
    • Michael, C.1    Ismail, M.2
  • 22
    • 0344317481 scopus 로고    scopus 로고
    • Design for yield of low power digital CMOS circuits
    • Budapest, September
    • M. Eisele, D. Schmitt-Landsiedel and J. Berthold, "Design for yield of low power digital CMOS circuits," Proc. ECCTD, pp. 906-911, Budapest, September 1997.
    • (1997) Proc. ECCTD , pp. 906-911
    • Eisele, M.1    Schmitt-Landsiedel, D.2    Berthold, J.3
  • 23
    • 0032114721 scopus 로고    scopus 로고
    • A low-voltage low-power wide-range CMOS variable gain amplifier
    • July
    • A. Motamed, C. Hwang, and M. Ismail, "A low-voltage low-power wide-range CMOS variable gain amplifier," IEEE Trans. Circuits and Syst. II, vol. 45, pp. 800-811, July 1998.
    • (1998) IEEE Trans. Circuits and Syst. II , vol.45 , pp. 800-811
    • Motamed, A.1    Hwang, C.2    Ismail, M.3
  • 25
    • 0022737957 scopus 로고
    • A versatile CMOS linear transconductor/square-law function circuit
    • E. Seevinck and R.F. Wassenaar, "A versatile CMOS linear transconductor/square-law function circuit," IEEE J. Solid-State Circuits, vol. SC-22, pp. 366-377, 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , pp. 366-377
    • Seevinck, E.1    Wassenaar, R.F.2
  • 27
    • 33748255247 scopus 로고    scopus 로고
    • APLAC-An Object Oriented Analog Circuit Simulator and Design Tool
    • Helsinki University of Technology, Circuit Theory Laboratory and Nokia Research Center, APLAC-An Object Oriented Analog Circuit Simulator and Design Tool, 7.1 User's Manual and Reference Manual, 1997.
    • (1997) 7.1 User's Manual and Reference Manual


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.