VLSI parallel architecture of a piecewise linear neural network for nonlinear channel equalization

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn 3, Issue , 1999, Pages 1629-1634

  Vidal, Martin ^a   Massicotte, Daniel ^a  

^a UNIVERSITÉ DU QUÉBEC À TROIS RIVIÈRES   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; FUNCTIONS; INVERSE PROBLEMS; MULTILAYER NEURAL NETWORKS; PIECEWISE LINEAR TECHNIQUES; PIPELINE PROCESSING SYSTEMS; PROBLEM SOLVING; VLSI CIRCUITS;

NONLINEAR CHANNEL EQUALIZATION;

COMMUNICATION CHANNELS (INFORMATION THEORY);

EID: 0032675977     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (15)