-
2
-
-
0026155912
-
-
May 1991.
-
H. Kobayashi, L. White, and A. Abidi, "An active resistor network for Gaussian filtering of images," IEEE J. SolidState Circuits, vol.26, no.5, pp.738-748, May 1991.
-
L. White, and A. Abidi, "An Active Resistor Network for Gaussian Filtering of Images," IEEE J. SolidState Circuits, Vol.26, No.5, Pp.738-748
-
-
Kobayashi, H.1
-
3
-
-
85027193845
-
-
Sept. 1992.
-
T. Shimmi, II. Kobayashi, T. Yagi, T. Sawaji, T. Matsumoto, and A. Abidi, "A parallel analog CMOS signal processor for image contrast enhancement," Proc. European Solid-State Circuits Conf., Copenhagen, Denmark, pp.163-166, Sept. 1992.
-
II. Kobayashi, T. Yagi, T. Sawaji, T. Matsumoto, and A. Abidi, "A Parallel Analog CMOS Signal Processor for Image Contrast Enhancement," Proc. European Solid-State Circuits Conf., Copenhagen, Denmark, Pp.163-166
-
-
Shimmi, T.1
-
4
-
-
0027845433
-
-
1993.
-
I. Takayanagi, T. Isokawa, and F. Nakamura, "A multiple output CMD imager for real-time image procesing," IEDM Dig. Tech., 22.5.1, pp.579-582, 1993.
-
T. Isokawa, and F. Nakamura, "A Multiple Output CMD Imager for Real-time Image Procesing," IEDM Dig. Tech., 22.5.1, Pp.579-582
-
-
Takayanagi, I.1
-
5
-
-
0028392939
-
-
1994.
-
S. Mendis, S. Kemcny, and E. Possum, "CMOS active pixel image sensor," IEEE Trans. Electron Devices, vol.41, pp.452-453, 1994.
-
S. Kemcny, and E. Possum, "CMOS Active Pixel Image Sensor," IEEE Trans. Electron Devices, Vol.41, Pp.452-453
-
-
Mendis, S.1
-
6
-
-
84999114983
-
-
Nov. 1994.
-
K. Aizawa, II. Ohno, T. Hamamoto, M. Hatori, and J. Yamazaki, "A novel image sensor for video compression," Proc. IEEE Int. Conf. Image Processing, Austin, Texas, vol.III, pp.591-595, Nov. 1994.
-
II. Ohno, T. Hamamoto, M. Hatori, and J. Yamazaki, "A Novel Image Sensor for Video Compression," Proc. IEEE Int. Conf. Image Processing, Austin, Texas, Vol.III, Pp.591-595
-
-
Aizawa, K.1
-
7
-
-
0029252076
-
-
Feb. 1995.
-
E. Lange, E. Funatsu, J. Ohta, and K. Kyuma, "Direct image processing using arrays of variable-sensitivity photodetectors," ISSCC Dig. Tech. Papers, San Francisco, pp.228-229, Feb. 1995.
-
E. Funatsu, J. Ohta, and K. Kyuma, "Direct Image Processing Using Arrays of Variable-sensitivity Photodetectors," ISSCC Dig. Tech. Papers, San Francisco, Pp.228-229
-
-
Lange, E.1
-
8
-
-
0027627707
-
-
July 1993.
-
J. Hakkarainen and H. Lee, "A 40 x 40 CCD/CMOS absolute-value-of-difference processor for use in a stereo vision system," IEEE J. Solid-State Circuit, vol.28, no.7, pp.799-807, July 1993.
-
And H. Lee, "A 40 X 40 CCD/CMOS Absolute-value-of-difference Processor for Use in A Stereo Vision System," IEEE J. Solid-State Circuit, Vol.28, No.7, Pp.799-807
-
-
Hakkarainen, J.1
-
9
-
-
0029069073
-
-
Jan. 1995.
-
H. Kobayashi, T. Matsumoto, T. Yagi, and K. Tanaka, "Light-adaptive architectures for regularization vision chips," Neural Networks, vol.8, no.l, pp.87-101, Jan. 1995.
-
T. Matsumoto, T. Yagi, and K. Tanaka, "Light-adaptive Architectures for Regularization Vision Chips," Neural Networks, Vol.8, No.l, Pp.87-101
-
-
Kobayashi, H.1
-
10
-
-
0027152475
-
-
1993.
-
M. Tremblay, M. d'Anjou, and D. Poussart, "Hexagonal sensor with imbedded analog image processing for pattern recognition," Proc. ICCC, pp.12.7.1-12.7.4, 1993.
-
M. D'Anjou, and D. Poussart, "Hexagonal Sensor with Imbedded Analog Image Processing for Pattern Recognition," Proc. ICCC, Pp.12.7.1-12.7.4
-
-
Tremblay, M.1
-
11
-
-
0026917197
-
-
1992.
-
J. Wyatt, et. al., "Analog VLSI systems for image acquisition and fast early vision," Int. J. Computer Vision, vol.8, no.3, pp.217-230, 1992.
-
Et. Al., "Analog VLSI Systems for Image Acquisition and Fast Early Vision," Int. J. Computer Vision, Vol.8, No.3, Pp.217-230
-
-
Wyatt, J.1
-
13
-
-
85027118591
-
-
Nov. 1994.
-
T. Sakai, T. Sawaji, and -T. Matsumoto, "The weak string filter and its implementation with i/MOS transistors," ITE Tech. Report, vol.18, no.68, pp.13-18, Nov. 1994.
-
T. Sawaji, and -T. Matsumoto, "The Weak String Filter and Its Implementation with I/MOS Transistors," ITE Tech. Report, Vol.18, No.68, Pp.13-18
-
-
Sakai, T.1
-
14
-
-
85027095447
-
-
Sept. 1994.
-
T. Matsumoto and K. Kondo, "Realization of the 'weak rod' by a double layer parallel network," Neural Computation, vol.6, no.5, pp.944-956, Sept. 1994.
-
And K. Kondo, "Realization of the 'Weak Rod' by A Double Layer Parallel Network," Neural Computation, Vol.6, No.5, Pp.944-956
-
-
Matsumoto, T.1
-
15
-
-
0031332529
-
-
Dec. 1997.
-
S. Kawahito, M. Yoshida, M. Sasaki, K. Umehara, D. Miyazaki, Y. Tadokoro, K. Murata, S. Doushou, and A. Matsuzawa, "A CMOS image sensor with analog twodimensional DCT-based compression circuits for one-chip cameras," IEEE J. Solid-State Circuits, vol.32, no.12, pp.2030-2041, Dec. 1997.
-
M. Yoshida, M. Sasaki, K. Umehara, D. Miyazaki, Y. Tadokoro, K. Murata, S. Doushou, and A. Matsuzawa, "A CMOS Image Sensor with Analog Twodimensional DCT-based Compression Circuits for One-chip Cameras," IEEE J. Solid-State Circuits, Vol.32, No.12, Pp.2030-2041
-
-
Kawahito, S.1
-
16
-
-
0027624863
-
-
July 1993.
-
T. Bernard, B. Zavidovique, and F. Devos, "A programmable artificial retina," IEEE J. Solid-State Circuits, vol.28, no.7, pp.789-798, July 1993.
-
B. Zavidovique, and F. Devos, "A Programmable Artificial Retina," IEEE J. Solid-State Circuits, Vol.28, No.7, Pp.789-798
-
-
Bernard, T.1
-
17
-
-
85027115453
-
-
May 1991.
-
M. Ishikawa, "Parallel processing for sensory information," IEICE Trans., vol.J74-C-II, no.5, pp.255-266, May 1991.
-
"Parallel Processing for Sensory Information," IEICE Trans., Vol.J74-C-II, No.5, Pp.255-266
-
-
Ishikawa, M.1
-
18
-
-
27944492851
-
-
1992.
-
T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations," IEEE Trans. Electron Devices, vol.39, pp.1444-1455, 1992.
-
And T. Ohmi, "A Functional MOS Transistor Featuring Gate-level Weighted Sum and Threshold Operations," IEEE Trans. Electron Devices, Vol.39, Pp.1444-1455
-
-
Shibata, T.1
-
19
-
-
85027171726
-
-
April 1997.
-
T. Sakai, H. Nagai, and T. Matsumoto, "An analog convolution circuit with floating gates and its applications," Proc. IEICE 10th Karuizawa Workshop on Circuits and Systems, Karuizawa, Japan, pp.41-46, April 1997.
-
H. Nagai, and T. Matsumoto, "An Analog Convolution Circuit with Floating Gates and Its Applications," Proc. IEICE 10th Karuizawa Workshop on Circuits and Systems, Karuizawa, Japan, Pp.41-46
-
-
Sakai, T.1
-
20
-
-
84891788250
-
-
Feb. 1998.
-
T. Sawaji, T. Sakai, H. Nagai, and T. Matsumoto, "Implementation of resistive fuse with floating gate MOS transistors," J. ITE, vol.52, no.2, pp.200-205, Feb. 1998.
-
T. Sakai, H. Nagai, and T. Matsumoto, "Implementation of Resistive Fuse with Floating Gate MOS Transistors," J. ITE, Vol.52, No.2, Pp.200-205
-
-
Sawaji, T.1
|