Minimum cut linear arrangement of p-q dgs for VLSI layout of adder trees

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E82-A, Issue 5, 1999, Pages 767-774

  Takagu, Kazuyoshi ^a   Takagi, Naofumi ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Adder tree; Graph algorithm; Minimum cut linear arrangement; Multiplier; Vlsi layout

Indexed keywords

ADDERS; APPROXIMATION THEORY; DYNAMIC PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; TREES (MATHEMATICS); VLSI CIRCUITS;

GRAPH ALGORITHM; MINIMUM CUT LINEAR ARRANGEMENT;

ALGORITHMS;

EID: 0032668750     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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