Scalability analysis for conservative simulation of logical circuits

VLSI Design

Volumn 9, Issue 3, 1999, Pages 219-235

  Keller, Jörg ^a,d,e   Rauber, Thomas ^b,d   Rederlechner, Bernd ^c,d,f  

^a UNIVERSITY OF HAGEN   (Germany)

^b MARTIN LUTHER UNIVERSITY HALLE WITTENBERG   (Germany)

^c Telekom Entwicklungszentrum Sudwest   (Germany)

^d SAARLAND UNIVERSITY   (Germany)

^e University Saarbrücken ^*  (Germany)

^f Entwicklungszentrum Süd West   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; DATA STRUCTURES; ESTIMATION; LOGIC DESIGN; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

DISCRETE EVENT SIMULATION; SHARED MEMORY MULTIPROCESSORS;

LOGIC CIRCUITS;

EID: 0032665641     PISSN: 1065514X     EISSN: None     Source Type: None    
DOI: 10.1155/1999/14802     Document Type: Article

References (28)

1. Abolhassan, F., Drefenstedt, R., Keller, J., Paul, W. J. and Scheerer, D. (1993). "On the physical design of PRAMs," Computer Journal, 36(8), 756-762.
2. Almasi, G. and Gottlieb, A. (1994). "Highy Parallel Computing," Redwood City, CA: Benjamin/Cummings, 2nd edition.
3. Avril, H. and Tropper, C., "Clustered time warp and logic simulation," Proc. 9th Workshop on Paralle and Distributed Simulation, Lake Placid, NY, June 1995, pp. 112-119.
4. Bailey, M. L. (1992). "A time based model for investigating parallel logic-level simulation," IEEE Transactions on Computer-Aided Design, 11, 814-824.
5. Bailey, M. L., Briner, J. V. Jr. and Chamberlain, R. D. (1994). "Parallel Logic Simulation of VLSI Systems," ACM Computing Reviews, 26(3), 255-294.
6. Baker, W. I., Herath, J., Jayasumana, A. and Mahmood, A., "A logic simulation engine based on a modified data flow architecture," Proc. IEEE International Conf. on Computer Aided Design ICCAD-92, Santa Clara CA, November 1992, pp. 377-380.
7. Baker, W. I. and Mahmood, A., "An analysis of parallel synchronous and conservative asynchronous logic simulation schemes," Proc. 6th IEEE Symposium on Parallel and Distributed Processing, Dallas, TX, December 1994, pp. 92-99.
8. Berry, O. and Jefferson, D., "Critical path analysis of distributed simulation," Proc. 1985 SCS Multiconference on Distributed Simulation, San Diego, CA, January 1985, pp. 57-60.
9. Boukerche, A. and Trapper, C., "A Static Partitioning and Mapping Algorithm for Conservative Parallel Simulations," Proc. 8th Workshop on Parallel and Distributed Simulation, Edinburgh, Scotland, UK, July 1994, pp. 164-172.
10. Bryant, R. E. (1977). "Simulation of packet communications architecture computer systems," Technical Report MIT-LCS-TR-188, Massachusetts Institute of Technology.
11. Chandy, K. M. and Misra, J. (1979). "Deadlock absence proofs for networks of communicating processes," Information Processing Letters, 94, 185-189.
12. Chandy, K. M. and Misra, J. (1981). "Asynchronous distributed simulation via a sequence of parallel computations," Communications of the ACM, 24(11), 198-206.
13. Fujimoto, R. M. (1990). "Parallel discrete event simulation," Communications of the ACM, 33(10), 30-53.
14. Grün, T., Rauber, T. and Röhrig, J., "The programming environment of the SB-PRAM," Proc. 7th IASTED ISMM Intl. Conf on Parallel and Distributed Computing and Systems, Washington D. C., October 1995.
15. Gunter, M. A., "Understanding supercritical speedup," Proc. of 1993 Winter Simulation Conference, Los Angeles, CA, December 1993, pp. 81-87.
16. Jefferson, D. R. (1985). "Virtual time," ACM Transactions of Programming Languages and Systems, 7(3), 404-425.
17. Jefferson, D. and Reiher, P., "Supereritical speedup," Proc. of 24th Annual Simulation Symposium, New Orleans, LA, April 1991, pp. 159-168.
18. Kapp, K. L., Hartrum, T. C. and Wailes, T. S., "An improved cost function for static partitioning of parallel circuit simulations using a conservative synchronization protocol," Proc. 9th Workshop on Parallel and Distributed Simulation, Lake Placid, NY, June 1995, pp. 78-85.
19. Konas, P. and Yew, P.-C., "Partitioning for synchronous parallel simulation," Proc. 9th Workshop on Parallel and Distributed Simulation, Lake Placid, NY, June 1995, pp. 181-184.
20. Lenoski, D., Laudon, J., Gharachorloo, K., Weber, W.-D., Gupta, A., Hennessy, J., Horowitz, M. and Lam, M. S., "The Stanford DASH multiprocessor," IEEE Computer, 25(3), 63-79, March 1992.
21. Lin, Y.-B. (1992). "Parallelism analyzers for parallel discrete event simulation," ACM Transactions on Modeling and Computer Simulation, 2(3), 239-264.
22. Livny, M., "A study of parallelism in distributed simulation," Proc. of 1985 SCS Multiconference on Distributed Simulation, San Diego, CA, January 1985, pp. 94-98.
23. Röhrig, J. (1996). "Implementation of the P4 Runtime Library on the SB-PRAM (in German)," Master's Thesis, Universität des Saarlandes.
24. Singh, J. P., Weber, W.-D. and Gupta, A. (1992). "SPLASH: Stanford Parallel Applications for Shared-Memory," Computer Architecture News, 20(1), 5-44.
25. Sleator, D. D. and Tarjan, R. E. (1985). "Self-adjusting binary search trees," Journal of the ACM, 32(3), 652-686.
26. Soulé, L., "Parallel Logic Simulation: An Evaluation of Centralized-Time and Distributed-Time Algorithms," Ph. D. Thesis, Stanford University, June 1992.
27. Sporrer, C. and Bauer, H., "Corolla partitioning for distributed logic simulation of VLSI-circuits," Proc. 7th Workshop on Parallel and Distributed Simulation, San Diego, CA, May 1993, pp. 85-92.
28. Sterling, T., Savarese, D., Merkey, P. and Olson, K., "An Empirical Study of the Convex SPP-1000 Hierarchical Shared-Memory System," Proc. International Confreduce on Parallel Architectures and Compilation Techniques PACT '95, Limassol, Cyprus, June 1995.