Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies

Electronics Letters

Volumn 35, Issue 2, 1999, Pages 112-113

  Moisiadis, Y ^a   Bouras, I ^b   Papadas, C ^a   Schoellkopf, J P ^c  

^a Integrated Systems Development   (Greece)

^b INSTITUTE OF MICROELECTRONICS   (Greece)

^c STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; STANDARDS; THRESHOLD VOLTAGE;

TRANSIENT SELF BACK-BIASED (TSBB) TECHNIQUE;

BUFFER CIRCUITS;

EID: 0032663944     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19990116     Document Type: Article

References (4)

1. SETA, K., HARA, H., KURODA, T., KAKUMU, M., and SAKURAI, T.: '50% active power saving without speed degradation using standby power reduction (SPR) circuit'. ISSCC Dig. Tech. Papers, February 1995, pp. 318-319
2. 2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme', IEEE J. Solid State Circuits. 1996, 31, (11), pp. 1770-1779
3. MUTOH, S., DOUSEKI, T., MATSUYA, Y., AOKI, T., SHIGEMATSU, S., and YAMADA, J.: '1V power supply high-speed digital circuit technology with multithreshold-voltage CMOS', IEEE J. Solid State Circuits, 1995, 30, (8), pp. 847-854
4. WADA, Y., UEDA, K., HIROTA, T., HIRANO, Y., MASHIKO, K., and HAMANO, H.: 'Active body-bias SOI-CMOS driver circuits'. Symp. on VLSI Circuits Dig. Technical Papers, 1997, pp. 29-30