Timing-driven global routing for standard-cell VLSI design

Computer Systems Science and Engineering

Volumn 14, Issue 3, 1999, Pages 175-185

  Youssef, Habib ^a   Sait, Sadiq M ^a  

^a KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; SIMULATED ANNEALING;

TABU SEARCH;

VLSI CIRCUITS;

EID: 0032661922     PISSN: 02676192     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (17)

1. Sait, SM and Youssef, H VLSI Physical Design Automation: Theory and Practice, McGraw-Hill (also co-published by IEEE Press) (1995)
2. Cong, J and Preas, B 'A new algorithm for standard-cell global routing', Proc. IEEE Int. Conf. Computer Aided Design (November 1988) pp 176-179
3. Glover, F 'Tabu Search-Part I', ORSA J. Computing, 1 (1989) pp 190-206
4. Glover, F Tabu Search-Part II', ORSA J. Computing, 1 (1990) pp 4-32
5. Glover, F 'Heuristics for integer programming using surrogate constraints', Decision Science (1993), pp 156-166
6. Vecchi, MP and Kirkpatrick, S 'Global wiring by simulated annealing', Shoukoudo (July 1987) pp 215-222
7. Sugai, Y and Hirata, H 'A global router for standard-cell VLSI with feed-through assignment optimization', Electronics and Communications in Japan (1990)
8. Sechen, C and Sangiovanni-Vincentelli, A L Timber-Wolf3.2: A new standard-cell placement and global routing package', Proceedings of 23rd Design Automation Conference (1992) pp 432-439
9. Cong, J 'Provably good performance-driven global routing', IEEE Trans. Computer-Aided Design (June (1992) pp 739-752
10. Youssef, H, Lin, R and Shragowitz, E 'Bounds on net delays for VLSI circuits', IEEE Trans. CAS, 39(11) (November 1992) pp 815-824
11. Youssef, H, Sutanthavibul, S and Shragowitz, E 'Pre-Layout Timing Analysis of Cell-Based VLSI Design', Computer-Aided Design Journal, 24(7) (July 1992) pp 367-379
12. Nair, R et al. 'Generation of performance constraints for layout', IEEE Trans. Computer-Aided Design, 8(8) (August 1989) pp 860-874
13. Metropolis, M et al. 'Equation of state calculation by fast computing machines', Journal of Chemical Physics (1953) pp 1087-1092
14. Sait, SM and Youssef, H Iterative Computer Algorithms and Their Applications in Engineering, IEEE Press (1999)
15. Sugai, Y and Hirata, H 'A hierarchical simulated annealing method for VLSI block placement problem', Trans. Institute of Electronics, Information and Communication Engineers (1988) pp 760-767
16. Fukao, T 'Distributed System Theory', IEEE Trans. Computer-Aided Design (October 1983)
17. Kozminski, K OASIS: Open Architecture Silicon Implementation Software,Users Guide. MCNC Center for Microelectronics, North Carolina (October 1992)