Limits of digital testing for dynamic circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 28-32

  Adams, R Dean ^a   Cooley, Edmond S ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; ERROR DETECTION; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; VLSI CIRCUITS;

DIGITAL TESTING; DYNAMIC CIRCUITS; FAULT MODEL REDUCTION TECHNIQUE; STATIC AND GATES; STUCK-AT TESTS;

INTEGRATED CIRCUIT TESTING;

EID: 0032661191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (9)