Flexible path selection procedure for path delay fault testing

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 152-159

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

PATH DELAY FAULT TESTING; PATH SELECTION PROCEDURE;

INTEGRATED CIRCUIT TESTING;

EID: 0032661189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (10)