Implication and evaluation techniques for proving fault equivalence

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 201-207

  Amyeen, M Enamul ^a   Fuchs, W Kent ^a   Pomeranz, Irith ^a   Boppana, Vamsi ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; EQUIVALENCE CLASSES; FAILURE ANALYSIS; LOGIC CIRCUITS;

DIAGNOSTIC FAULT EQUIVALENCE; DIAGNOSTIC TEST PATTERN GENERATION;

INTEGRATED CIRCUIT TESTING;

EID: 0032660965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (17)