Use of a WLR technique to characterize voiding in 0.25 and 0.18 μm technologies for integrated circuits

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 1999, Pages 291-295

  Marathe, Amit ^a   Besser, Paul ^a   Tsiang, Jerry ^a   Tran, Khanh ^a   Pham, Van ^a   Tracy, Bryan ^a   Fang, Peng ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ELECTROMIGRATION; ETCHING; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DEVICES; METALLIZING; MONITORING; RELIABILITY; SILICON WAFERS; TESTING; TITANIUM NITRIDE;

ISOTHERMAL WAFER LEVEL TEST; METAL STACK; SUBMICRON INTERCONNECT LINES; VOID DETECTION; VOIDING; WAFER LEVEL RELIABILITY TEST;

VLSI CIRCUITS;

EID: 0032659629     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (10)