High performance analog and digital PLL design

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1999, Pages

  Almeida, Teresa M ^a   Piedade, Moises S ^a  

^a INESC   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL MODELS;

ANALOG PHASE LOCKED LOOPS (APLL); DIGITAL PHASE LOCKED LOOPS (DPLL);

PHASE LOCKED LOOPS;

EID: 0032655923     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)