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Volumn , Issue , 1999, Pages 112-120
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Procedural texture mapping on FPGAs
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Author keywords
[No Author keywords available]
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Indexed keywords
LOGIC DESIGN;
THREE DIMENSIONAL COMPUTER GRAPHICS;
HARDWARE TEXTURE MAPPING;
PERLIN NOISE;
FIELD PROGRAMMABLE GATE ARRAYS;
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EID: 0032655794
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/296399.296438 Document Type: Article |
Times cited : (20)
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References (18)
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