Process optimization and integration for silicon oxide intermetal dielectric planarized by chemical mechanical polish

Journal of the Electrochemical Society

Volumn 146, Issue 5, 1999, Pages 1984-1990

  Lin, Chi Fa ^a   Tseng, Wei Tsu ^b   Feng, Ming Shiann ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL POLISHING; DIELECTRIC FILMS; OXIDES; SEMICONDUCTING SILICON COMPOUNDS;

CHEMICAL MECHANICAL POLISHING; INTERMETAL DIELECTRIC PLANARIZATION;

SEMICONDUCTING FILMS;

EID: 0032655148     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.1391877     Document Type: Article

References (18)

1. S. Sivaram, H. Bath, R. Leggett, A. Maury, K. Monnig, and R. Tolles, Solid State Technol., 35-5, 87 (1992).
2. M. S. Phadke, Proc. Amer. Statistical Assoc., p. 11 (1982).
3. M. S. Phadke, Quality Engineering Using Robust Design, Prentice Hall, Englewood Cliffs, NJ (1989).
4. T. K. Yu, C. C. Yu, and M. Orlowski, Tech. Dig. Int. Electron Devices Meet., 35.4.1 (1994).
5. L. M. Cook, J. Non-Cryst. Solids, 120, 152 (1990).
6. W. Li, D. W. Shin, M. Tomozawa, and S. P. Murarka, Thin Solid Films, 270, 601 (1995).
7. S. M. Jang, S. L. Hsu, L. M. Liu, M. S. Lin, F. Y. Tsi, and B. T. Dai, Proceedings of Int. Electron Device Mater. Symp., p. 11-40-160 (1994).
8. F. Preston, J. Soc. Glass Technol., 11, 214 (1927).
9. W.-T. Tseng and Y.-L. Wang, J. Electrochem. Soc., 144, L15 (1997).
10. W.-T. Tseng, Y.-S. Wang, J.-H. Chin, W.-C. Pan, in Chemical Mechanical Planarization in Integrated Circuit Device Manufacturing, S. Raghavan, R. L. Opila, and L. Zhang, Editors, PV 98-7, p. 98, The Electrochemical Society Proceedings Series, Pennington, NJ (1998).
11. A. Modak, P. Monteith, and N. Parekh, in Proceedings of 2nd International CMP VLSI/ULSI Multilevel Interconnection Conference (CMP-MIC), p. 169 (1997).
12. A. Maury and V. Czitrom, in Proceedings of 1st International CMP VLSI/ULSI Multilevel Interconnection Conf. (CMP-MIC), p. 285 (1996).
13. C.-H. Liu, Master Thesis, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan (1995).
14. W.-T. Tseng, in Proceedings of Advanced Metallization and Interconnect Systems for ULSI Applications-1997, p. 617 (1998).
15. J. Grillaert, H. Meynen, J. Waeterloos, and B. Coenegrachts, in Proceedings of Advanced Metallization and Interconnect Systems for ULSI Applications-1996, p. 525 (1997).
16. P. Burke, in Proceedings of VLSI Multilevel Interconnect Conference, p. 379 (1991).
17. B. Stine, D. Ouma, R. Divecha, D. Boning, J. Chung, D. L. Hetherington, I. Ali, G. Shinn, J. Clark, O. S. Nakagawa, and S.-Y. Oh, in Proceedings of 2nd International CMP for ULSI Multilevel Interconnect Conference (CMP-MIC), p. 26 (1997).
18. O. S. Nakagawa, S.-Y. Oh, F. Eschbach, G. Ray, P. Nikkel, P. R. Divecha, B. E. Stine, D. O. Ouma, D. S. Boing, and J. E. Chung, in Proceedings of Advanced Metallization and Interconnect Systems for ULSI Applications-1997, p. 543 (1997).