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Volumn 45, Issue 10, 1999, Pages 809-824

A high level FPGA-based abstract machine for image processing

Author keywords

Custom computing; Digital image processing; FPGA's; High performance architectures

Indexed keywords

ALGORITHMS; COMPUTER SYSTEMS PROGRAMMING; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE PROCESSING; RESPONSE TIME (COMPUTER SYSTEMS);

EID: 0032652957     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1383-7621(98)00040-X     Document Type: Article
Times cited : (11)

References (22)
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  • 10
    • 0025448487 scopus 로고
    • IAL: A parallel image processing programming language
    • Crookes D., Morrow P.J., McParland P.J. IAL: A parallel image processing programming language. IEE Proceedings. 137(3):1990;176-182.
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    • 0028397502 scopus 로고
    • A high level language for image processing
    • Brown T.J., Crookes D. A high level language for image processing. Image and Vision Computing. 12(2):1994;67-79.
    • (1994) Image and Vision Computing , vol.12 , Issue.2 , pp. 67-79
    • Brown, T.J.1    Crookes, D.2
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    • Plessey, PDSP16488 Single Chip Convolver with integral line delay, Technical report, Plessey Semiconductors Ltd., Cheney Manor, Swindon, Wiltshire SN2 2QW, UK
    • Plessey, PDSP16488 Single Chip Convolver with integral line delay, Technical report, Plessey Semiconductors Ltd., Cheney Manor, Swindon, Wiltshire SN2 2QW, UK, 1988.
    • (1988)
  • 14
    • 0037541389 scopus 로고
    • Parameterised Convolution Filtering in an FPGA, More FPGAs
    • W. Moore, W. Luk (Eds.)
    • R.G. Shoup, Parameterised Convolution Filtering in an FPGA, More FPGAs, W. Moore, W. Luk (Eds.), Abington EE&CS Books, 1994, pp. 274.
    • (1994) Abington EE&CS Books , pp. 274
    • Shoup, R.G.1
  • 16
    • 0027311507 scopus 로고
    • A defect-tolerant systolic array implementation for real-time image processing
    • Hecht V., Ronner K., Pirsch P. A defect-tolerant systolic array implementation for real-time image processing. Journal of VLSI signal processing. 5:1993;37-47.
    • (1993) Journal of VLSI Signal Processing , vol.5 , pp. 37-47
    • Hecht, V.1    Ronner, K.2    Pirsch, P.3
  • 17
    • 0028485282 scopus 로고
    • Hybrid signed-digit number systems: A unified framework for redundant number representations with bounded carry propagation chains
    • Phatak D., Koren I. Hybrid signed-digit number systems: A unified framework for redundant number representations with bounded carry propagation chains. IEEE Computer. 43(8):1994;880-891.
    • (1994) IEEE Computer , vol.43 , Issue.8 , pp. 880-891
    • Phatak, D.1    Koren, I.2
  • 18
    • 0037879394 scopus 로고
    • Design of a high performance IIR digital filter chip
    • Woods R.F., McCanny J.V. Design of a high performance IIR digital filter chip. IEE Proceedings-E. 139(3):1992;195-202.
    • (1992) IEE Proceedings-E , vol.139 , Issue.3 , pp. 195-202
    • Woods, R.F.1    McCanny, J.V.2
  • 19
    • 0011213584 scopus 로고
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.