Tuning logic simulators for timing analysis

Electronics Letters

Volumn 35, Issue 10, 1999, Pages 800-802

  Maksimovic D M ^a   Litovski, V B ^a  

^a UNIVERSITY OF NI   (Serbia)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; MATHEMATICAL MODELS;

LOGIC SIMULATORS; SOFTWARE PACKAGE ALECSIS;

LOGIC DESIGN;

EID: 0032647292     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19990545     Document Type: Article

References (5)

1. OUSTERHOUT, J.K.: 'CRYSTAL: A timing analyzer for NMOS VLSI circuits', Proc. 3rd Caltech Conf. on VLSI, March 1983, pp. 57-69
2. JOUPPI, N.: 'TV: An NMOS timing analyzer',Proc. 3rd Caltech Conf. VLSI, March 1983, pp. 71-85
3. OH, C., and MERCER, M.R.: 'Efficient logic-level timing analysis using constraint-guided critical path search', IEEE Trans. VLSI Syst., 1996, 4, (3), pp. 346-355
4. BERGE, J., FONKOUA, A., MAGINOT, S., and ROUILLARD, J.: 'VHDL'92' (Kluwer Academic Publishers, 1993)
5. MR Č ARICA, Ž., GLOZIĆ, D., LITOVSKI, V., MAKSIMOVIĆ, D., Ć, T., and GAVRILOVIĆ, D.: 'Alecsis 2.3 - the simulator for circuits and systems: User's manual', (LEDA 1/1998), http://leda.elfak.ni.ac.yu