A self-timed ICT chip for image coding

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 9, Issue 6, 1999, Pages 856-860

  Pang, Tin Chak Johnson ^a   Choy, Chiu Sing Oliver ^a   Chan, Cheong Fat ^a   Cham, Wai Kuen ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Asynchronous; Image coding; Integer cosine transform; Micropipeline; Self timed logic; Very large scale integration (VLSI) design

Indexed keywords

CMOS INTEGRATED CIRCUITS; COSINE TRANSFORMS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; TIMING CIRCUITS; VLSI CIRCUITS;

INTEGER COSINE TRANSFORMS (ICT);

IMAGE CODING;

EID: 0032646840     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.785723     Document Type: Article

References (8)

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5. J. Spares, C. D. Nielsen, L. S. Nielsen, and J. Staunstrup, "Design of self-timed multipliers: A comparison," presented at the Workshop on Asynchronous Design Methodologies, Manchester, U.K., Mar. 1993.
6. S. Hauck, "Asynchronous design methodologies: An overview," Proc. IEEE, vol. 83, pp. 69-93, Jan. 1995.
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8. W. K. Cham, "Development of integer cosine transforms by the principle of dyadic symmetry," Proc. Inst. Elect. Eng., vol. 136, pt. 1, no. 4, Aug. 1989.